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1. 发明授权

US06893967B1 L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials 有权
标题翻译：使用无定形碳或CVD有机材料结合或图案化的L形间隔物
公开(公告)号：US06893967B1
公开(公告)日：2005-05-17
申请号：US10755911
申请日：2004-01-13
申请人： Marilyn I. Wright , Douglas J. Bonser , Lu You , Kay Hellig
发明人： Marilyn I. Wright , Douglas J. Bonser , Lu You , Kay Hellig
IPC分类号： H01L29/72
CPC分类号： H01L29/6656
摘要： A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected by a layer of CVD organic material or amorphous carbon. The CVD organic material or amorphous carbon is then patterned using the patterned protective material as a mask. The chemistry used to pattern the CVD organic material or amorphous carbon is relatively harmless to the underlying substrate. Alternatively, an L-shaped spacer is patterned without using a photoresist mask by forming an amorphous carbon spacer around a gate that is covered with a conformal layer of a conventional spacer material. The conventional spacer material is patterned using the amorphous carbon spacer as an etch mask. The amorphous carbon spacer is easily formed without the need for lithographic patterning, and therefore this method is preferable to methods using photoresist masks.
摘要翻译：多层L型间隔件由包含CVD有机材料或无定形碳的下部和由保护材料构成的上部形成。使用光致抗蚀剂掩模对上部进行图案化。在该图案化期间，下面的衬底被CVD有机材料层或无定形碳保护。然后使用图案化的保护材料作为掩模对CVD有机材料或无定形碳进行图案化。用于对CVD有机材料或无定形碳进行图案化学的化学物质对于底层基材相对无害。或者，通过在被常规间隔物材料的共形层覆盖的栅极周围形成无定形碳隔离物，将L形间隔物图案化而不使用光致抗蚀剂掩模。使用无定形碳间隔物作为蚀刻掩模来对传统的间隔物材料进行图案化。非晶碳隔离物容易地形成而不需要平版印刷图案，因此该方法优于使用光致抗蚀剂掩模的方法。

2. 发明授权

US06881616B1 System for forming a semiconductor device and method thereof including implanting through a L shaped spacer to form source and drain regions 有权
标题翻译：用于形成半导体器件的系统及其方法，包括通过L形间隔物注入以形成源区和漏区
公开(公告)号：US06881616B1
公开(公告)日：2005-04-19
申请号：US10058854
申请日：2002-01-28
申请人： Kay Hellig , Douglas J. Bonser , Wen-Jie Qi
发明人： Kay Hellig , Douglas J. Bonser , Wen-Jie Qi
IPC分类号： H01L21/311 , H01L21/336 , H01L21/338 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/31116 , H01L21/823425 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.
摘要翻译：公开了一种在制造集成电路器件中制造侧壁间隔物的方法。在半导体衬底上形成电介质间隔层。在形成电介质层之后的层之前蚀刻电介质间隔层，以形成L形间隔物。在另一个实施例中，在衬底上形成结构，该结构具有基本上垂直于衬底表面的侧壁部分。介电层形成在衬底上。间隔物形成在电介质层的一部分上并与结构的侧壁部分相邻，其中绝缘层上的至少一部分电介质层没有上覆的氧化物间隔物是电介质的未被保护的部分。去除介电层的未保护部分的至少一部分。通过控制厚度和/或源极漏极掺杂水平，可以在L形间隔物的一部分之下形成中间源极 - 漏极区。

3. 发明授权

US06673635B1 Method for alignment mark formation for a shallow trench isolation process 有权
标题翻译：浅沟槽隔离工艺的对准标记形成方法
公开(公告)号：US06673635B1
公开(公告)日：2004-01-06
申请号：US10185780
申请日：2002-06-28
申请人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
发明人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2100
CPC分类号： H01L23/544 , H01L21/30604 , H01L21/3083 , H01L21/31116 , H01L21/31144 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.
摘要翻译：提出了用于制造所需深度的对准特征以及绝缘体上硅（SOI）材料中的浅沟槽隔离（STI）特征的方法。具体实施方案要求不超过两个光刻和蚀刻工艺，其代表了需要三次光刻和蚀刻工艺的电流方法的改进，以便在制造半导体器件期间产生期望的特征。

4. 发明授权

US06979651B1 Method for forming alignment features and back-side contacts with fewer lithography and etch steps 有权
标题翻译：用较少光刻和蚀刻步骤形成对准特征和背面接触的方法
公开(公告)号：US06979651B1
公开(公告)日：2005-12-27
申请号：US10207653
申请日：2002-07-29
申请人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
发明人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/308 , H01L21/311 , H01L21/762 , H01L23/544
CPC分类号： H01L21/76264 , H01L21/3081 , H01L21/31144 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a dielectric material to form the isolation. A second lithography and etch step is then applied to etch the window locations for back-side contacts, and to transfer the alignment marks down into the SOI lower substrate. After this first lithography and etch step, the alignment marks in the top silicon may be used for alignment of the second lithography mask and etch. This is made possible by leaving the polish stop layer on the wafer, which serves to increase the optically effective thickness of the alignment mark pattern. The polish stop layer is removed after the second etch process. The teachings can be applied to any Semiconductor-On-Insulator-type wafer/technology where the top semiconductor layer is not thicker than the optimum alignment mark depth.
摘要翻译：该方法执行第一次光刻和蚀刻，以将浅沟槽隔离特征和对准标记特征形成到顶部SOI层中。然后用介电材料填充浅沟槽以形成隔离。然后施加第二光刻和蚀刻步骤以蚀刻用于背面接触的窗口位置，并将对准标记向下转移到SOI下基板中。在该第一光刻和蚀刻步骤之后，顶部硅中的对准标记可用于对准第二光刻掩模和蚀刻。这可以通过将抛光停止层留在晶片上来实现，其用于增加对准标记图案的光学有效厚度。在第二次蚀刻工艺之后去除抛光停止层。该教导可以应用于任何半导体绝缘体型晶片/技术，其中顶部半导体层不比最佳对准标记深度厚。

5. 发明申请

US20050118801A1 Technique for forming a gate electrode by using a hard mask 失效
标题翻译：通过使用硬掩模形成栅电极的技术
公开(公告)号：US20050118801A1
公开(公告)日：2005-06-02
申请号：US10974119
申请日：2004-10-27
申请人： Massud Aminpur , Kay Hellig
发明人： Massud Aminpur , Kay Hellig
IPC分类号： H01L21/28 , H01L21/332 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66553 , H01L21/28123 , H01L29/78
摘要： The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.
摘要翻译：用于形成诸如栅电极的电路元件的各向异性蚀刻工艺通过使用硬掩模而不是抗蚀剂特征来实现，从而在需要临界尺寸时避免复杂的抗蚀剂修整过程，这远远低于所涉及的光刻的分辨率。此外，临界尺寸可以通过沉积工艺而不是通过抗蚀剂修整工艺来调节。

6. 发明授权

US06699641B1 Photosensitive bottom anti-reflective coating 有权
标题翻译：感光底部防反射涂层
公开(公告)号：US06699641B1
公开(公告)日：2004-03-02
申请号：US10021828
申请日：2001-12-12
申请人： Kay Hellig , Massud Aminpur
发明人： Kay Hellig , Massud Aminpur
IPC分类号： G03C500
CPC分类号： H01L21/0274 , G03F7/091 , G03F7/095 , H01L21/0276
摘要： Various circuit structures incorporating masks and anti-reflective coatings and methods of fabricating the same are provided. In one aspect, a circuit structure is provided that includes a substrate and a first photosensitive film on the substrate. The first photosensitive film is photosensitive to a first electromagnetic spectrum and anti-reflective of a second electromagnetic spectrum that differs from the first electromagnetic spectrum. A second photosensitive film is on the first photosensitive film. The second photosensitive film is photosensitive to the second electromagnetic spectrum whereby exposure by the second electromagnetic spectrum will activate the second photosensitive film but not the first photosensitive film and exposure by the first electromagnetic spectrum will activate unmasked portions of the first photosensitive film. The first photosensitive film doubles as an anti-reflective coating that may be patterned anisotropically using lithographic techniques.
摘要翻译：提供了包含掩模和抗反射涂层的各种电路结构及其制造方法。在一个方面，提供一种电路结构，其包括基板和在基板上的第一感光膜。第一感光膜对第一电磁光谱和第一电磁光谱不同的第二电磁光谱的抗反射感光。第二感光膜位于第一感光膜上。第二感光膜对第二电磁光谱感光，由此通过第二电磁光谱的曝光将激活第二感光膜而不是第一感光膜，并且通过第一电磁光谱的曝光将激活第一感光膜的未屏蔽部分。第一感光膜兼作抗反射涂层，其可以使用光刻技术各向异性地进行图案化。

7. 发明授权

US07256113B1 System for forming a semiconductor device and method thereof 有权
标题翻译：用于形成半导体器件的系统及其方法
公开(公告)号：US07256113B1
公开(公告)日：2007-08-14
申请号：US10058708
申请日：2002-01-28
申请人： Kay Hellig , Phillip E. Crabtree , Massud Aminpur
发明人： Kay Hellig , Phillip E. Crabtree , Massud Aminpur
IPC分类号： H01L21/28
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66598 , H01L29/7833
摘要： A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.
摘要翻译：公开了一种在制造集成电路器件中制造侧壁间隔物的方法。在半导体衬底上形成电介质间隔层。在形成电介质层之后的层之前蚀刻电介质间隔层，以形成L形间隔物。在另一个实施例中，在衬底上形成结构，该结构具有基本上垂直于衬底表面的侧壁部分。介电层形成在衬底上。间隔物形成在电介质层的一部分上并与结构的侧壁部分相邻，其中绝缘层上的至少一部分电介质层没有上覆的氧化物间隔物是电介质的未被保护的部分。去除介电层的未保护部分的至少一部分。通过控制厚度和/或源极漏极掺杂水平，可以在L形间隔物的一部分之下形成中间源极 - 漏极区。

8. 发明授权

US07130762B2 Method and system for handling substrates in a production line including a cluster tool and a metrology tool 有权
标题翻译：在包括集群工具和计量工具的生产线中处理基板的方法和系统
公开(公告)号：US07130762B2
公开(公告)日：2006-10-31
申请号：US10360314
申请日：2003-02-07
申请人： Kay Hellig , Peter Goerigk , Uwe Liebold , Ronald Gruenz , Karl-Heinz Fandrey
发明人： Kay Hellig , Peter Goerigk , Uwe Liebold , Ronald Gruenz , Karl-Heinz Fandrey
IPC分类号： G06F17/18 , G06F19/00
CPC分类号： H01L21/67276 , G03F7/70533 , G03F7/70625 , G05B19/41865 , G05B2219/32049 , G05B2219/32059 , Y02P90/20 , Y02P90/22
摘要： In a production line, a cluster tool having a plurality of substantially identical process modules and a metrology tool includes a control unit that allows one to receive, store and process information that indicates in which process module which substrates have been processed and which selects, on the basis of the process information, which substrate has to be subjected to a measurement. Advantageously, the substrates are selected so that each process module is represented by a corresponding substrate to be measured in order to reliably monitor the process quality of each process module.
摘要翻译：在生产线中，具有多个基本上相同的处理模块和计量工具的集群工具包括一个控制单元，该控制单元允许一个接收，存储和处理信息，该信息指示在哪个过程模块中已处理哪些衬底以及哪个衬底被选择过程信息的基础，哪个基板必须进行测量。有利地，选择基板，使得每个处理模块由要测量的相应基板表示，以便可靠地监测每个处理模块的工艺质量。

9. 发明授权

US06696334B1 Method for formation of a differential offset spacer 有权
标题翻译：形成差动偏移间隔物的方法
公开(公告)号：US06696334B1
公开(公告)日：2004-02-24
申请号：US10260485
申请日：2002-09-30
申请人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
发明人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.
摘要翻译：提出了一种适用于掺入高级CMOS技术设备的制造工艺中的差分偏移间隔物形成方法。该方法包括形成覆盖多个栅极结构的第一绝缘层，然后形成覆盖第一绝缘层的第二绝缘层。形成掩模以暴露覆盖第一晶体管类型的栅极结构的第二绝缘层的第一部分，并且保护覆盖第二晶体管类型的晶体管的栅极结构的第二绝缘层的第二部分。然后蚀刻覆盖第一类型的栅极结构的第二绝缘层的暴露的第一部分。在蚀刻之后，去除掩模，并且蚀刻第二绝缘层和第一绝缘层的暴露的第二部分以形成邻接栅极结构的差分间隔物。端点用于停止间隔物蚀刻工艺。

10. 发明授权

US07962459B2 Method of providing context specific recipes in a semiconductor facility by defining product categories 有权
标题翻译：通过定义产品类别在半导体设备中提供上下文特定配方的方法
公开(公告)号：US07962459B2
公开(公告)日：2011-06-14
申请号：US10745044
申请日：2003-12-23
申请人： Kay Hellig , Ronald Grünz , Heiko Wagner , Uwe Liebold
发明人： Kay Hellig , Ronald Grünz , Heiko Wagner , Uwe Liebold
IPC分类号： G06F17/30
CPC分类号： G05B19/41865 , G05B2219/31418 , G05B2219/45026 , G06Q10/06 , Y02P90/20 , Y02P90/265
摘要： The RMS database for a semiconductor process line is established on the basis of product groups or categories, wherein all members of a category are linked by a common feature, such as a common basic design or a common basic technology. Common process recipes in a specified category may then be set up only once, thereby reducing the amount of effort for establishing the database. Moreover, new product types may be readily incorporated into the categories, thereby enabling the employment of the already-established category-specific context information.
摘要翻译：用于半导体工艺线的RMS数据库是基于产品组或类别建立的，其中类别的所有成员通过共同特征（诸如通用基本设计或公共基本技术）连接。然后可以将指定类别中的公共进程配方设置一次，从而减少建立数据库的工作量。此外，新产品类型可以容易地并入到类别中，从而使得能够使用已经建立的类别特定的上下文信息。

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