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1. 发明授权

US08564089B2 Electronic fuse structure formed using a metal gate electrode material stack configuration 有权
标题翻译：使用金属栅电极材料堆叠配置形成的电子熔丝结构
公开(公告)号：US08564089B2
公开(公告)日：2013-10-22
申请号：US12941595
申请日：2010-11-08
申请人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
发明人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.
摘要翻译：在复杂的半导体器件中，可以通过使用铝材料作为用于在电子熔丝中诱导电迁移的有效金属的替代栅极方法来提供电子熔丝。电子熔断器可以形成在隔离结构上，从而提供电子熔断器与半导体材料和衬底材料的有效的热解耦，从而使得能够以大体积配置提供有效的电子保险丝，同时避免将熔丝引入金属化系统。

2. 发明授权

US07192881B2 Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity 有权
标题翻译：通过增加蚀刻选择性来形成用于电路元件的侧壁间隔元件的方法
公开(公告)号：US07192881B2
公开(公告)日：2007-03-20
申请号：US10987466
申请日：2004-11-12
申请人： Thorsten Kammler , Karsten Wieczorek , Christoph Schwan
发明人： Thorsten Kammler , Karsten Wieczorek , Christoph Schwan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/6659 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/02318 , H01L21/31116 , H01L21/31612 , H01L29/665 , H01L29/6656
摘要： By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.
摘要翻译：通过在图案化氮化硅间隔层之前热处理二氧化硅衬垫，二氧化硅相对于氮化硅的蚀刻选择性增加，从而减少或消除了通过二氧化硅层的点蚀问题。这允许进一步缩放器件，其中需要非常薄的二氧化硅衬垫以获得漏极和源极区域中的掺杂剂分布图的精确横向图案化。

3. 发明申请

US20070001203A1 SEMICONDUCTOR DEVICE INCLUDING A VERTICAL DECOUPLING CAPACITOR 有权
标题翻译：半导体器件，包括垂直去耦电容器
公开(公告)号：US20070001203A1
公开(公告)日：2007-01-04
申请号：US11379605
申请日：2006-04-21
申请人： MATTHIAS LEHR , Kai Frohberg , Christoph Schwan
发明人： MATTHIAS LEHR , Kai Frohberg , Christoph Schwan
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/0629
摘要： A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also provides enhanced pattern uniformity during the highly critical gate patterning process.
摘要翻译：提供了用于去耦电容器的垂直或三维非平面配置，这大大减少了高电荷载流子存储容量的电容器所需的管芯面积。去耦电容器的非平面配置还在高度关键的栅极图案化工艺期间提供增强的图案均匀性。

4. 发明授权

US07005358B2 Technique for forming recessed sidewall spacers for a polysilicon line 有权
标题翻译：用于形成多晶硅线路的凹陷侧壁间隔物的技术
公开(公告)号：US07005358B2
公开(公告)日：2006-02-28
申请号：US10786401
申请日：2004-02-25
申请人： Thorsten Kammler , Katja Huy , Christoph Schwan
发明人： Thorsten Kammler , Katja Huy , Christoph Schwan
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.
摘要翻译：在形成复杂的场效应晶体管的双间隔或多间隔方法中，栅极电极的上侧壁部分可以在外间隔元件的凹陷期间被有效地暴露，因为外间隔件基本上由相同的材料组成作为衬垫材料。因此，用于凹陷外侧壁间隔件的各向异性蚀刻工艺还有效地去除了上侧壁部分上的衬垫残留物，并为难熔金属提供了增加的扩散路径。此外，可以通过相应地控制用于去除氧化物残余物的各向同性蚀刻工艺来增加漏极和源极区域上的硅化物区域的横向延伸。

5. 发明授权

US06696334B1 Method for formation of a differential offset spacer 有权
标题翻译：形成差动偏移间隔物的方法
公开(公告)号：US06696334B1
公开(公告)日：2004-02-24
申请号：US10260485
申请日：2002-09-30
申请人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
发明人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.
摘要翻译：提出了一种适用于掺入高级CMOS技术设备的制造工艺中的差分偏移间隔物形成方法。该方法包括形成覆盖多个栅极结构的第一绝缘层，然后形成覆盖第一绝缘层的第二绝缘层。形成掩模以暴露覆盖第一晶体管类型的栅极结构的第二绝缘层的第一部分，并且保护覆盖第二晶体管类型的晶体管的栅极结构的第二绝缘层的第二部分。然后蚀刻覆盖第一类型的栅极结构的第二绝缘层的暴露的第一部分。在蚀刻之后，去除掩模，并且蚀刻第二绝缘层和第一绝缘层的暴露的第二部分以形成邻接栅极结构的差分间隔物。端点用于停止间隔物蚀刻工艺。

6. 发明授权

US08806824B2 Wall construction and component for the same 有权
标题翻译：墙面施工和组件相同
公开(公告)号：US08806824B2
公开(公告)日：2014-08-19
申请号：US10518369
申请日：2002-06-19
申请人： Christoph Schwan
发明人： Christoph Schwan
IPC分类号： E04B1/74
CPC分类号： E04B2/02 , E04B1/7612 , E04B2002/0286
摘要： The present invention relates to a wall construction for an exterior brick wall of a building, comprising a rear brickwork and a front brickwork, which is characterized in that the front brickwork (2) is made at least in part of constructional elements (11), particularly bricks, building blocks and the like, which at their side facing the rear brickwork (5) are designed to be reflective for heat radiation. The invention further relates to a constructional element, in particular a brick, a building block or the like, for use in the production of the front brickwork of such a wall construction which on the side which in the walled-in state faces inwardly, is provided with a layer (8) which is reflective for heat radiation.
摘要翻译：本发明涉及一种用于建筑物的外墙砖的墙体结构，其包括后砖砌块和前砌砖，其特征在于，所述前砖砌件（2）至少部分由结构元件（11）制成，特别是在其面向后砖砌（5）的一侧的砖，构件等被设计为反射用于热辐射。本发明还涉及一种结构元件，特别是砖，建筑物块等，用于生产这种墙体结构的前砌砖，其在侧壁内侧面向内侧面为设置有反射用于热辐射的层（8）。

7. 发明授权

US08609485B2 Methods of forming efuse devices 有权
标题翻译：形成efuse器件的方法
公开(公告)号：US08609485B2
公开(公告)日：2013-12-17
申请号：US12941185
申请日：2010-11-08
申请人： Andreas Kurz , Andy Wei , Christoph Schwan
发明人： Andreas Kurz , Andy Wei , Christoph Schwan
IPC分类号： H01L21/8238
CPC分类号： H01L23/5256 , H01L21/28518 , H01L27/0629 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses.
摘要翻译：可以通过将电子熔丝适当地嵌入到具有降低的导热性的半导体材料中，在具有大体积配置的复杂半导体器件中提供半导体基电子熔断器。例如，可以在硅基材中提供硅/锗熔丝区域。因此，可以在大容量装置上的替代栅极接近的基础上形成复杂的栅极电极结构，而不影响电子熔断器的电子特性。

8. 发明申请

US20100025772A1 SEMICONDUCTOR DEVICE COMPRISING A SILICON/GERMANIUM RESISTOR 有权
标题翻译：包含硅/锗电阻的半导体器件
公开(公告)号：US20100025772A1
公开(公告)日：2010-02-04
申请号：US12477365
申请日：2009-06-03
申请人： Andreas Kurz , Roman Boschke , Christoph Schwan , John Morgan
发明人： Andreas Kurz , Roman Boschke , Christoph Schwan , John Morgan
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0802 , H01L27/0629 , H01L27/13 , H01L28/20
摘要： In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also reducing overall cycle times.
摘要翻译：在集成电路中，可以在硅/锗材料的基础上形成电阻器，从而提供降低的电阻率，这可以减小电阻元件的尺寸。此外，可以使用减少的掺杂剂浓度，其可以允许增加的工艺窗口来调节电阻值，同时还减少总的循环时间。

9. 发明授权

US07064071B2 Method of forming a conformal spacer adjacent to a gate electrode structure 有权
标题翻译：形成与栅电极结构相邻的共形间隔物的方法
公开(公告)号：US07064071B2
公开(公告)日：2006-06-20
申请号：US10813317
申请日：2004-03-30
申请人： Christoph Schwan
发明人： Christoph Schwan
IPC分类号： H01L21/311 , H01L21/336
CPC分类号： H01L29/6653 , H01L21/823864 , H01L29/6656
摘要： In a process for forming L-shaped sidewall spacers for a conducive line element, such as a gate electrode structure, the sacrificial spacers are formed of a material having a similar etch behavior as the material of the finally obtained L-shaped spacer, thereby improving tool utilization and reducing process complexity compared to conventional processes. In one particular embodiment, a spacer layer stack is provided having a first etch stop layer, a first spacer layer, a second etch stop layer, and a second spacer layer, wherein the first and second spacer layers are comprised of silicon nitride.
摘要翻译：在用于形成诸如栅极电极结构的导电线路元件的L形侧壁间隔物的方法中，牺牲隔离物由具有与最终获得的L形间隔物的材料相似的蚀刻行为的材料形成，由此改善工具利用率和降低流程复杂性与传统工艺相比。在一个特定实施例中，提供了具有第一蚀刻停止层，第一间隔层，第二蚀刻停止层和第二间隔层的间隔层堆叠，其中第一和第二间隔层由氮化硅构成。

10. 发明授权

US07005305B2 Signal layer for generating characteristic optical plasma emissions 有权
标题翻译：用于产生特征光学等离子体发射的信号层
公开(公告)号：US07005305B2
公开(公告)日：2006-02-28
申请号：US10447877
申请日：2003-05-29
申请人： Gunter Grasshoff , Christoph Schwan , Matthias Schaller
发明人： Gunter Grasshoff , Christoph Schwan , Matthias Schaller
IPC分类号： H01L21/00
CPC分类号： H01J37/32963 , H01L21/31116
摘要： A technique is provided that may be used to improve optical endpoint detection in a plasma etch process. A semiconductor structure is manufactured that includes at least one electrical device. The technique is adapted for forming a signal layer on or in a wafer, wherein the signal layer comprises a chemical element that causes a characteristic optical emission when coming into contact with an etch plasma. The chemical element does not have a primary influence on the electrical properties of the electrical device. The signal layer is for use in a plasma etch process to detect a plasma etch endpoint if the characteristic optical emission is detected. The signal layer may be patterned and may be incorporated into a stop layer.
摘要翻译：提供了可用于改进等离子体蚀刻工艺中的光学端点检测的技术。制造包括至少一个电气装置的半导体结构。该技术适于在晶片上或晶片中形成信号层，其中信号层包括当与蚀刻等离子体接触时引起特征光发射的化学元素。化学元素对电气设备的电气性能没有主要影响。如果检测到特征光发射，则信号层用于等离子体蚀刻工艺中以检测等离子体蚀刻端点。信号层可以被图案化并且可以结合到停止层中。

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