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1. 发明申请

US20150170986A1 SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING 有权
标题翻译：具有隔离墙的半导体封装件可减少电磁耦合
公开(公告)号：US20150170986A1
公开(公告)日：2015-06-18
申请号：US14104870
申请日：2013-12-12
申请人： Margaret A. Szymanowski , Sarmad K. Musa , Fernando A. Santos , Mahesh K. Shah
发明人： Margaret A. Szymanowski , Sarmad K. Musa , Fernando A. Santos , Mahesh K. Shah
IPC分类号： H01L23/31 , H01L23/495 , H03F3/213 , H01L21/48 , H03F1/02 , H01L23/552 , H01L21/56
CPC分类号： H03F1/0288 , H01L21/4821 , H01L23/3121 , H01L23/492 , H01L23/49541 , H01L23/49575 , H01L23/552 , H01L23/66 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/0655 , H01L25/50 , H01L2223/6611 , H01L2223/6644 , H01L2224/48091 , H01L2224/48106 , H01L2224/48195 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/3011 , H01L2924/3025 , H03F3/195 , H03F3/211 , H03F3/213 , H03F2200/451 , H03F2203/21106 , H01L2924/00 , H01L2224/45099
摘要： A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
摘要翻译：提出了一种用于封装包括壁以减少电磁耦合的半导体器件的系统和方法。半导体器件具有基板，第一电路和第二电路在其上彼此靠近地形成。导电材料的隔离壁位于第一电路和第二电路之间，隔离壁被配置为在半导体器件的操作期间减小第一和第二电路之间的电感耦合。介绍了几种类型的隔离墙。

2. 发明授权

US09673162B2 High power semiconductor package subsystems 有权
公开(公告)号：US09673162B2
公开(公告)日：2017-06-06
申请号：US13613979
申请日：2012-09-13
申请人： Lakshminarayan Viswanathan , Scott M. Hayes , Scott D. Marshall , Mahesh K. Shah
发明人： Lakshminarayan Viswanathan , Scott M. Hayes , Scott D. Marshall , Mahesh K. Shah
IPC分类号： H01L29/10 , H01L23/00 , H01L23/367 , H01L23/538 , H01L23/498 , H01L23/31 , H01L21/56
CPC分类号： H01L24/24 , H01L21/561 , H01L23/3121 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/32 , H01L24/82 , H01L24/83 , H01L2224/24137 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/92247 , H01L2924/10253 , H01L2924/12042 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.

3. 发明授权

US07332414B2 Chemical die singulation technique 有权
标题翻译：化学模切技术
公开(公告)号：US07332414B2
公开(公告)日：2008-02-19
申请号：US11159553
申请日：2005-06-22
申请人： Brian W. Condie , David J. Dougherty , Mahesh K. Shah
发明人： Brian W. Condie , David J. Dougherty , Mahesh K. Shah
IPC分类号： H01L21/00
CPC分类号： H01L21/78
摘要： A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a first die section (210), a second die section (212) adjacent the first die section (210), and a strip (216) connecting the first die section (210) and the second die section (212), removing material from portions of the non-active surface of the substrate (206) on which the backing material (104) is not deposited to thereby partially separate the substrate (200) into a first die (236) and a second die (238) connected to one another by the strip (254) of the deposited backing material, and breaking the strip connector (254) to separate the first die (236) from the second die (238).
摘要翻译：提供了一种从具有有源表面（204）和非有效表面（206）的衬底（200）制造半导体器件的方法。该方法包括以图案（500）将背衬材料（104）沉积到基底（206）的非活性表面上，图案（500）具有至少第一模具部分（210），第二模具部分 212），以及连接第一模具部分（210）和第二模具部分（212）的条带（216），从衬底（206）的非活性表面的部分去除材料，其上不沉积背衬材料（104），从而通过沉积的背衬材料的带（254）将衬底（200）部分地分离成第一模具（236）和第二模具（238），所述第一模具（238）彼此连接，以及断开带状连接器（254）以将第一管芯（236）与第二管芯（238）分离。

4. 发明授权

US5918112A Semiconductor component and method of fabrication 失效
标题翻译：半导体元件及制造方法
公开(公告)号：US5918112A
公开(公告)日：1999-06-29
申请号：US899672
申请日：1997-07-24
申请人： Mahesh K. Shah , John W. Hart, Jr.
发明人： Mahesh K. Shah , John W. Hart, Jr.
IPC分类号： H01L25/18 , G01P1/02 , H01L23/31 , H01L25/04 , H01L21/44
CPC分类号： H01L23/3107 , G01P1/02 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247
摘要： A semiconductor component includes a leadframe (10), an electronic component (21) mounted over the leadframe (10), a packaging material (23) around the electronic component (21) and the leadframe (10) wherein the packaging material has a recess (24), another electronic component (30) in the recess (24), and a cap (32) over the recess (24) and the other electronic component (30). The other electronic component (30) is electrically coupled to the electronic component (21) through internal leads (13) and (14) of the leadframe (10). After a dam bar (15) is removed from the leadframe (10), the internal leads (13) are physically and electrically isolated from other portions of the leadframe (10) including the external leads (12) and the flag (11).
摘要翻译：半导体部件包括引线框架（10），安装在引线框架（10）上的电子部件（21），围绕电子部件（21）和引线框架（10）的包装材料（23），其中包装材料具有凹部（24），凹部（24）中的另一个电子部件（30），以及位于凹部（24）和另一个电子部件（30）之上的盖子（32）。另一个电子部件（30）通过引线框架（10）的内部引线（13）和（14）电耦合到电子元件（21）。在从引线框架（10）移除阻挡条（15）之后，内部引线（13）与包括外部引线（12）和标记（11）的引线框架（10）的其他部分物理和电气隔离。

5. 发明授权

US07701074B2 Semiconductor device with a buffer region with tightly-packed filler particles 失效
标题翻译：半导体器件具有紧密填充填料颗粒的缓冲区
公开(公告)号：US07701074B2
公开(公告)日：2010-04-20
申请号：US12204500
申请日：2008-09-04
申请人： Brian W. Condie , L. M. Mahalingam , Mahesh K. Shah
发明人： Brian W. Condie , L. M. Mahalingam , Mahesh K. Shah
IPC分类号： H01L23/29
CPC分类号： H01L23/3135 , H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/05553 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.
摘要翻译：半导体器件的实施例包括支撑构件，安装在支撑构件的一部分上的半导体管芯，缓冲区域和塑料封装。缓冲区域覆盖模具的一部分，并且包括填充在树脂内的树脂和填料颗粒。填料颗粒具有填料尺寸的混合物并且紧密地包装在树脂内。缓冲区具有第一介电常数和第一损耗角正切。塑料封装包围支撑构件和模具的至少一部分。塑料封装包括第二介电常数和第二损耗角正切的塑料材料，其中第二介电常数大于第一介电常数，第二损耗角正切大于第一损耗角正切。

6. 发明授权

US09538659B2 Solder wettable flanges and devices and systems incorporating solder wettable flanges 有权
标题翻译：焊接可润湿法兰和装有焊接可湿性法兰的装置和系统
公开(公告)号：US09538659B2
公开(公告)日：2017-01-03
申请号：US13972838
申请日：2013-08-21
申请人： Lakshminarayan Viswanathan , Jaynal A. Molla , Mahesh K. Shah
发明人： Lakshminarayan Viswanathan , Jaynal A. Molla , Mahesh K. Shah
IPC分类号： H01R9/00 , H05K1/18 , B23K1/20 , H05K1/14 , H05K1/05
CPC分类号： H05K1/181 , B23K1/20 , H01L2224/48091 , H01L2924/19107 , H05K1/056 , H05K1/141 , H05K2201/10015 , H05K2201/10166 , H05K2201/10416 , H05K2201/10553 , H05K2203/1173 , Y02P70/611 , Y10T29/49144 , Y10T428/12389 , H01L2924/00014
摘要： An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.
摘要翻译：焊料可润湿凸缘的实施例包括由导电材料形成的凸缘体。凸缘体具有底表面，顶表面，在顶表面和底表面之间延伸的侧壁以及从底表面延伸到凸缘体中的一个或多个凹陷。每个凹陷由凹陷表面限定，凹陷表面可以或可以不是可焊料润湿的。在将凸缘焊接到基板期间，凹陷可以用作多余焊料的储存器。实施例还包括包括这种焊料可润湿凸缘的装置和系统，以及用于形成焊料可润湿凸缘，装置和系统的方法。

7. 发明申请

US20150055310A1 SOLDER WETTABLE FLANGES AND DEVICES AND SYSTEMS INCORPORATING SOLDER WETTABLE FLANGES 有权
标题翻译：焊接法兰和装置和系统，焊接焊接法兰法兰
公开(公告)号：US20150055310A1
公开(公告)日：2015-02-26
申请号：US13972838
申请日：2013-08-21
申请人： LAKSHMINARAYAN VISWANATHAN , Jaynal A. Molla , Mahesh K. Shah
发明人： LAKSHMINARAYAN VISWANATHAN , Jaynal A. Molla , Mahesh K. Shah
IPC分类号： H05K1/11 , H05K13/04 , H05K1/18 , B23K1/20
CPC分类号： H05K1/181 , B23K1/20 , H01L2224/48091 , H01L2924/19107 , H05K1/056 , H05K1/141 , H05K2201/10015 , H05K2201/10166 , H05K2201/10416 , H05K2201/10553 , H05K2203/1173 , Y02P70/611 , Y10T29/49144 , Y10T428/12389 , H01L2924/00014
摘要： An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.
摘要翻译：焊料可润湿凸缘的实施例包括由导电材料形成的凸缘体。凸缘体具有底表面，顶表面，在顶表面和底表面之间延伸的侧壁以及从底表面延伸到凸缘体中的一个或多个凹陷。每个凹陷由凹陷表面限定，凹陷表面可以或可以不是可焊料润湿的。在将凸缘焊接到基板期间，凹陷可以用作多余焊料的储存器。实施例还包括包括这种焊料可润湿凸缘的装置和系统，以及用于形成焊料可润湿凸缘，装置和系统的方法。

8. 发明申请

US20090001614A1 SEMICONDUCTOR DEVICE WITH A BUFFER REGION WITH TIGHTLY-PACKED FILLER PARTICLES 失效
标题翻译：带缓冲区的半导体器件，带有紧密包装的填料颗粒
公开(公告)号：US20090001614A1
公开(公告)日：2009-01-01
申请号：US12204500
申请日：2008-09-04
申请人： Brian W. Condie , Mali Mahalingam , Mahesh K. Shah
发明人： Brian W. Condie , Mali Mahalingam , Mahesh K. Shah
IPC分类号： H01L23/495 , H01L23/29
CPC分类号： H01L23/3135 , H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/05553 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.
摘要翻译：半导体器件的实施例包括支撑构件，安装在支撑构件的一部分上的半导体管芯，缓冲区域和塑料封装。缓冲区域覆盖模具的一部分，并且包括填充在树脂内的树脂和填料颗粒。填料颗粒具有填料尺寸的混合物并且紧密地包装在树脂内。缓冲区具有第一介电常数和第一损耗角正切。塑料封装包围支撑构件和模具的至少一部分。塑料封装包括第二介电常数和第二损耗角正切的塑料材料，其中第二介电常数大于第一介电常数，第二损耗角正切大于第一损耗角正切。

9. 发明授权

US07432133B2 Plastic packaged device with die interface layer 有权
标题翻译：带芯片接口层的塑料封装装置
公开(公告)号：US07432133B2
公开(公告)日：2008-10-07
申请号：US11257822
申请日：2005-10-24
申请人： Brian W. Condie , Mahesh K. Shah
发明人： Brian W. Condie , Mahesh K. Shah
IPC分类号： H01L21/48
CPC分类号： H01L23/3192 , H01L23/3164 , H01L23/3171 , H01L23/4334 , H01L24/97 , H01L2224/48091 , H01L2924/01004 , H01L2924/01005 , H01L2924/01021 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die are coated with the buffer layer. The buffer layer is patterned to expose the die bonding pads but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.
摘要翻译：提供了具有低介电常数和/或低损耗正切材料的缓冲层的塑料封装的半导体器件的结构和方法，其将管芯表面与塑料封装分开。具有基本上完成的SC管芯的半导体晶片被缓冲层涂覆。图案化缓冲层以露出芯片焊盘，但是将缓冲层留在其它芯片金属化部分或全部上。然后将管芯分离，安装在引线框架或其他支撑件上，引线键合或以其他方式耦合到外部引线，并封装。塑料封装围绕裸片和缓冲层，提供坚实的结构。缓冲层减少了裸片上的金属化区域之间的寄生电容，串扰和损耗。也可以在缓冲层和塑料封装之间的晶片台处设置可选的密封层，以减轻任何缓冲层孔隙率。

10. 发明授权

US5888412A Method for making a sculptured diaphragm 失效
标题翻译：制作雕刻膜片的方法
公开(公告)号：US5888412A
公开(公告)日：1999-03-30
申请号：US610033
申请日：1996-03-04
申请人： Kathirgamasundaram Sooriakumar , Andrew C. McNeil , Kenneth G. Goldman , Mahesh K. Shah
发明人： Kathirgamasundaram Sooriakumar , Andrew C. McNeil , Kenneth G. Goldman , Mahesh K. Shah
IPC分类号： G01L9/00 , B44C1/22
CPC分类号： G01L9/0042
摘要： A sculptured diaphragm of a sensor is fabricated by providing a semiconductor material, forming at least one cavity on the front side of the semiconductor material, forming a diaphragm layer over the semiconductor material, and the etching a cavity on the back side of the semiconductor material. If a sensor having a diaphragm with a central boss is desired, then the diaphragm layer is planarized to form a thick and a thin portion in the diaphragm layer.
摘要翻译：通过提供半导体材料制造传感器的雕刻隔膜，在半导体材料的正面上形成至少一个空腔，在半导体材料上形成隔膜层，并且蚀刻半导体材料背面的空腔。如果需要具有带有中心凸台的隔膜的传感器，则隔膜层被平坦化以在隔膜层中形成厚而薄的部分。

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