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1. 发明授权

US5465275A Efficient utilization of present state/next state registers 失效
标题翻译：高效利用当前状态/下一状态寄存器
公开(公告)号：US5465275A
公开(公告)日：1995-11-07
申请号：US153334
申请日：1993-11-16
申请人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
发明人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/45 , H04L25/08 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41
摘要： In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.
摘要翻译：根据本发明，一种用于在诸如通信系统或维特比解码器中确定下一状态累积成本的情况下有效利用存储器的技术。该系统包括具有分配给第一阵列的寄存器的一部分和分配给第二阵列的寄存器的一部分的存储器。该技术包括从第一阵列的存储寄存器检索当前状态累积成本，并基于当前状态累积成本计算下一状态累积成本。下一个状态累积成本被存储在第二阵列的存储寄存器中。第二个阵列被指定为包含当前状态累积成本。从第二阵列的存储寄存器检索当前状态累积成本，并用于计算后续的下一状态累积成本。随后的下一状态累积成本被存储在第一阵列的存储寄存器中。

2. 发明授权

US5559837A Efficient utilization of present state/next state registers 失效
公开(公告)号：US5559837A
公开(公告)日：1996-09-24
申请号：US488274
申请日：1995-06-07
申请人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
发明人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/45 , H04L25/08 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41
摘要： In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

3. 发明授权

US5432804A Digital processor and viterbi decoder having shared memory 失效
标题翻译：具有共享存储器的数字处理器和维特比解码器
公开(公告)号：US5432804A
公开(公告)日：1995-07-11
申请号：US153405
申请日：1993-11-16
申请人： Marc S. Diamondstein , Homayoon Sam , Mark E. Thierbach
发明人： Marc S. Diamondstein , Homayoon Sam , Mark E. Thierbach
IPC分类号： G06F11/10 , G06F12/00 , H03M13/23 , H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/6569
摘要： An integrated circuit includes a digital signal processor (DSP) and an error correction co-processor (ECCP) that implements a Viterbi decoding function. The DSP and ECCP share a block of multi-port memory, typically by bus multiplexing a dual-port RAM. When the ECCP possesses the RAM, it inhibits the DSP from accessing that block of the RAM by asserting an EBUSY flag. This technique conserves and optimizes the RAM usage, allowing the DSP and ECCP to advantageously be formed on the same integrated circuit chip.
摘要翻译：集成电路包括实现维特比解码功能的数字信号处理器（DSP）和纠错协处理器（ECCP）。 DSP和ECCP共享一块多端口存储器，通常通过总线复用双端口RAM。当ECCP拥有RAM时，它通过断言EBUSY标志来禁止DSP访问RAM的该块。这种技术可以节省和优化RAM的使用，从而使DSP和ECCP有利地形成在同一个集成电路芯片上。

4. 发明授权

US4399516A Stored-program control machine 失效
标题翻译：存储程序控制机
公开(公告)号：US4399516A
公开(公告)日：1983-08-16
申请号：US233143
申请日：1981-02-10
申请人： Donald E. Blahut , Marc L. Harrison , Michael J. Killian , Mark E. Thierbach
发明人： Donald E. Blahut , Marc L. Harrison , Michael J. Killian , Mark E. Thierbach
IPC分类号： G06F9/22 , G06F15/78
CPC分类号： G06F15/7832 , G06F9/223
摘要： A hierarchical organization of programmable logic arrays permits the control of microprocessor functions to be achieved in a way which allows otherwise wasted clock time to be used. The mostly independent operations of the several PLA's is organized by "handshake" signals from the latches of one PLA to those of another via AND circuits operative to selectively enable clock signals, in some instances, and data in other instances, to be applied to the latches. The use of the AND circuits enables requisite operations to be achieved with relatively small PLA's.
摘要翻译：可编程逻辑阵列的分级组织允许以允许使用时间浪费时间的方式来实现微处理器功能的控制。几个PLA的大部分独立操作是通过一个PLA的锁存器通过与另一个通道的“握手”信号通过AND电路组织的，电路在某些情况下有选择地启用时钟信号，并且在其他情况下将数据应用于锁存器使用AND电路可以通过相对较小的PLA实现必要的操作。

5. 发明授权

US5454014A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：US5454014A
公开(公告)日：1995-09-26
申请号：US152807
申请日：1993-11-16
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin , Mark E. Thierbach
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin , Mark E. Thierbach
IPC分类号： G06F17/10 , H03M13/41 , H04L27/00 , H03D1/00 , H04L27/06
CPC分类号： H03M13/6569 , G06F17/10 , H03M13/3961 , H03M13/41
摘要： A signal processor with an embedded Viterbi co-processor is disclosed. The Viterbi branch metric unit contains embedded metric units which calculate either Euclidean or Manhattan metrics for MLSE or deconvolution operations.
摘要翻译：公开了具有嵌入式维特比协处理器的信号处理器。维特比分支度量单位包含嵌入的度量单位，其计算用于MLSE或去卷积运算的欧几里德或曼哈顿度量。

6. 发明授权

US4661922A Programmed logic array with two-level control timing 失效
标题翻译：具有两级控制时序的编程逻辑阵列
公开(公告)号：US4661922A
公开(公告)日：1987-04-28
申请号：US448002
申请日：1982-12-08
申请人： Mark E. Thierbach
发明人： Mark E. Thierbach
IPC分类号： H03K3/037 , H03K19/177 , G06F9/28
CPC分类号： H03K3/0372 , H03K19/17716
摘要： A programmed logic array (PLA) is equipped with a first master-slave shift register on the intermediate wordlines (e.g., W.sub.1, W.sub.2 . . . W.sub.n) between AND and OR planes of the PLA and a second master-slave shift register on the output lines emanating from the OR plane. In this way, since the propagation delays of both AND and OR planes are much larger than those of the registers, the speed of operation of the PLA is limited to the greater of the propagation delays of the AND and OR plane instead of the sum of these delays as in prior art.
摘要翻译：编程逻辑阵列（PLA）在PLA与AND与OR平面之间的中间字线（例如W1，W2 ... Wn）上配备有第一主从移位寄存器，从OR平面发出的输出线。以这种方式，由于AND和OR平面的传播延迟远大于寄存器的传播延迟，所以PLA的操作速度被限制在AND和OR平面的传播延迟的较大值，而不是这些延迟如现有技术那样。

7. 发明授权

US06801995B1 Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes 失效
标题翻译：用于对具有多个指令可选择资源类型的数字处理器的一组指令代码进行最佳编码的方法和相关联的优化的指令代码组
公开(公告)号：US06801995B1
公开(公告)日：2004-10-05
申请号：US09129116
申请日：1998-08-04
申请人： Mazhar M. Alidina , Sivanand Simanapalli , Mark E. Thierbach
发明人： Mazhar M. Alidina , Sivanand Simanapalli , Mark E. Thierbach
IPC分类号： G06F900
CPC分类号： G06F8/447 , G06F9/30145 , G06F9/30149 , G06F9/30181
摘要： A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the particular resources used, where all of the instructions in a group have one or more resource types in common. The position of the highest order active bit in the code is used to identify which resource group a particular instruction belongs to. Instructions in a resource group reserve the same number of bits to identify the specific resources to be used, and no more bits are reserved than required. The remaining unassigned bits are used to encode particular command codes. When such an encoded command is decoded, the resource group is identified by determining the highest order active bit in the instruction. This information is used to determine which bits in the instruction are command bits and which are resource-identifying bits. The specific resource information is extracted and used to select the designated resources to be used in executing the command. This encoding scheme eliminates wasted bits in instructions and thereby increases the number of instructions which can be implemented.
摘要翻译：公开了一种将唯一指令代码分配给指令集中的指令的方法。还公开了这样的编码指令集。指令根据所使用的特定资源进行分组，其中组中的所有指令都具有一个或多个共同的资源类型。代码中最高有效位的位置用于标识特定指令属于哪个资源组。资源组中的指令保留相同数量的位以标识要使用的特定资源，并且不再保留比所需的更多位。剩余的未分配位用于编码特定的命令代码。当这样的编码命令被解码时，通过确定指令中的最高有效位来识别资源组。该信息用于确定指令中哪些位是命令位，哪些是资源标识位。提取特定资源信息并用于选择在执行命令时要使用的指定资源。该编码方案消除了指令中的浪费比特，从而增加了可以实现的指令数量。

8. 发明授权

US06530014B2 Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits 失效
标题翻译：具有最小编码位的近正交双MAC指令集架构
公开(公告)号：US06530014B2
公开(公告)日：2003-03-04
申请号：US09132882
申请日：1998-08-12
申请人： Mazhar M. Alidina , Mark E. Thierbach , Sivanand Simanapalli , Larry R. Tate
发明人： Mazhar M. Alidina , Mark E. Thierbach , Sivanand Simanapalli , Larry R. Tate
IPC分类号： G06F9302
CPC分类号： G06F9/3877 , G06F7/5443 , G06F9/30101 , G06F9/30145 , G06F9/3893
摘要： A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.
摘要翻译：提供了一个近正交的双MAC指令集，其实际上只使用65个命令来实现272个命令的正交指令集的整个功能。简化指令集是通过消除相对于命令结果的对称性的指令，并且通过对诸如程序员的数据呈现顺序之类的项目施加简单的限制来实现的。命令的具体选择也由与双MAC架构相关联的双字对齐的存储器体系结构确定。简化的指令集体系结构保留了命令集的功能和固有的并行性，并且要求比完全正交集更少的命令位实现。

9. 再颁专利

USRE32858E Stored-program control machine 失效
标题翻译：存储程序控制机
公开(公告)号：USRE32858E
公开(公告)日：1989-02-07
申请号：US766912
申请日：1985-08-16
申请人： Donald E. Blahut , Marc L. Harrison , Mark E. Thierbach
发明人： Donald E. Blahut , Marc L. Harrison , Mark E. Thierbach
IPC分类号： G06F9/22 , G06F15/78
CPC分类号： G06F9/223 , G06F15/7832
摘要： A hierarchical organization of programmable logic arrays permits the control of microprocessor functions to be achieved in a way which allows otherwise wasted clock time to be used. The mostly independent operations of the several PLA's is organized by "handshake" signals from the latches of one PLA to those of another via AND circuits operative to selectively enable clock signals, in some instances, and data in other instances, to be applied to the latches. The use of the AND circuits enables requisite operations to be achieved with relatively small PLA's.

10. 发明授权

US4493029A Microprocessor with PLA adapted to implement subroutines 失效
标题翻译：具有PLA的微处理器适用于实现子程序
公开(公告)号：US4493029A
公开(公告)日：1985-01-08
申请号：US378403
申请日：1982-05-14
申请人： Mark E. Thierbach
发明人： Mark E. Thierbach
IPC分类号： G06F9/22
CPC分类号： G06F9/223
摘要： A microprocessor includes a programmable logic array (PLA) adapted to allow "subroutines" or sequences within the PLA. The subroutines can be used by more than one opcode with a return performed to the opcode after execution of the subroutine.
摘要翻译：微处理器包括适于允许PLA内的“子程序”或序列的可编程逻辑阵列（PLA）。子程序可以由多个操作码使用，并在子程序执行后返回执行操作码。

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