专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5987490A Mac processor with efficient Viterbi ACS operation and automatic traceback store 失效
标题翻译： Mac处理器具有高效维特比ACS操作和自动追溯存储
公开(公告)号：US5987490A
公开(公告)日：1999-11-16
申请号：US970921
申请日：1997-11-14
申请人： Mazhar M. Alidina , Sivanand Simanapalli
发明人： Mazhar M. Alidina , Sivanand Simanapalli
IPC分类号： G06F9/315 , G06F9/30 , H03M13/23 , H03M13/41 , G06F7/38
CPC分类号： H03M13/6561 , H03M13/4107 , H03M13/4161 , H03M13/6569
摘要： A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and split-mode add, subtract, and compare operations. Viterbi compare operations are executed using the subtract function and the sign bit is combined with a compare mode bit to generate a traceback output which indicates the proper traceback bit to store. When a compare operation is performed and a Viterbi mode bit is active, each generated traceback output is shifted into a traceback register for later use in a Viterbi traceback routine.
摘要翻译：公开了一种双MAC处理器，其优化使得可以在两个机器周期中执行包括追溯位存储在内的两个维特比ACS操作。该处理器包括连接到公共累加器寄存器组的一对加法器运算逻辑单元，并且支持完全和分离模式的加，减和比较操作。使用减法函数执行维特比比较操作，并将符号位与比较模式位组合，以生成指示正确追溯位存储的追溯输出。当执行比较操作并且维特比模式位被激活时，每个产生的回溯输出被转移到追溯寄存器中，以供稍后在维特比回溯例程中使用。

2. 发明授权

US06272188B1 Single-cycle accelerator for extremun state search 失效
标题翻译：单循环加速器用于extremun状态搜索
公开(公告)号：US06272188B1
公开(公告)日：2001-08-07
申请号：US09074669
申请日：1998-05-08
申请人： Mohammad Shafiul Mobin , Sivanand Simanapalli , Larry R. Tate
发明人： Mohammad Shafiul Mobin , Sivanand Simanapalli , Larry R. Tate
IPC分类号： H04L2706
CPC分类号： H03M13/37 , G06F7/544 , H03M13/41 , H03M13/45
摘要： The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit and a multiplexer. The value from the group and the predetermined value are compared in the arithmetic logic unit. A selector is set to one of a first or second logic state. In the first logic state the selector selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag set by the comparison in the arithmetic logic unit and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to a first state and the value is less than the predetermined value. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to the second state and the value is greater than the predetermined value.
摘要翻译：本发明包括一种识别极值值和一组值中的每个值具有相关联索引的值的方法。计数寄存器初始化为初始计数。同时向算术逻辑单元和多路复用器提供来自组中的值以及预定值。在算术逻辑单元中比较来自组中的值和预定值。选择器被设置为第一或第二逻辑状态之一。在第一个逻辑状态下，选择器选择最小值; 在第二个逻辑状态下，选择器选择一个最大值。基于通过算术逻辑单元和选择器中的比较设置的标志，将值和预定值中的一个选择为极值。将预定值替换为极值，并且当选择器被设置为第一状态并且该值小于预定值时，存储计数寄存器计数。将预定值替换为极值，并且当选择器设置为第二状态并且该值大于预定值时，存储计数寄存器计数。

3. 发明授权

US6029267A Single-cycle, soft decision, compare-select operation using dual-add processor 失效
标题翻译：单周期，软判决，比较选择操作使用双加法处理器
公开(公告)号：US6029267A
公开(公告)日：2000-02-22
申请号：US977912
申请日：1997-11-25
申请人： Sivanand Simanapalli , Larry R. Tate
发明人： Sivanand Simanapalli , Larry R. Tate
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/12
CPC分类号： H03M13/37 , H03M13/41 , H03M13/45
摘要： In accordance with the invention, a method of generating a soft symbol confidence level for use in decoding a received digital signal includes calculating a difference between two potential next state accumulated costs to provide a soft symbol confidence level. Simultaneously with calculating the difference between two potential next state accumulated costs, performing a compare-select operation to identify one of the two potential next state accumulated costs as an extremum of the two present state accumulated costs.
摘要翻译：根据本发明，一种生成用于解码所接收的数字信号的软符号置信水平的方法包括计算两个潜在的下一状态累积成本之间的差以提供软符号置信水平。在计算两个潜在的下一状态累积成本之间的差异的同时，执行比较选择操作以将两个潜在的下一状态累积成本中的一个识别为两个当前状态累积成本的极值。

4. 发明授权

US6081921A Bit insertion approach to convolutional encoding 失效
标题翻译：卷插入方法进行卷积编码
公开(公告)号：US6081921A
公开(公告)日：2000-06-27
申请号：US974873
申请日：1997-11-20
申请人： Sivanand Simanapalli
发明人： Sivanand Simanapalli
IPC分类号： H03M13/23 , H03M13/03
CPC分类号： H03M13/23
摘要： A convolutional encoder and method convolutionally encode input bits from an input frame. The convolutional encoder has a predetermined bit input source and a logic circuit. The predetermined bit input source inserts a plurality of predetermined bits into an input register with the input bits. The logic circuit has a plurality of shift registers, a plurality of polynomial generators, and an output generator. The plurality of shift registers shift the input register, including the predetermined bits, to generate shifted data. The plurality of polynomial generators generate respective polynomial values in a plurality of polynomial registers from the shifted data. The output generator generates output data in an output register from the polynomial values corresponding to convolutional encoding of the data in the input register.
摘要翻译：卷积编码器和方法从输入帧卷积编码输入比特。卷积编码器具有预定位输入源和逻辑电路。预定位输入源将多个预定位插入到具有输入位的输入寄存器中。逻辑电路具有多个移位寄存器，多个多项式发生器和输出发生器。多个移位寄存器移位包括预定位的输入寄存器以产生移位数据。多个多项式生成器从移位数据生成多个多项式寄存器中的多项式值。输出发生器根据与输入寄存器中的数据的卷积编码对应的多项式值，在输出寄存器中生成输出数据。

5. 发明授权

US6064714A Shifter capable of split operation 失效
标题翻译：移动能力分裂操作
公开(公告)号：US6064714A
公开(公告)日：2000-05-16
申请号：US126991
申请日：1998-07-31
申请人： Mazhar M. Alidina , Geoffrey Francis Burns , Sivanand Simanapalli
发明人： Mazhar M. Alidina , Geoffrey Francis Burns , Sivanand Simanapalli
IPC分类号： G11C19/00 , G11C19/28
CPC分类号： G11C19/00 , G11C19/28
摘要： A device for shifting data in a cascade multiplexer shifter allows the shifter to be used in a full-length mode or in a split mode where the shifter is divided into two equal halves with upper and lower half fields thereof respectively receiving individual data numbers. Each data number is thereafter simultaneously shifted right or shifted left a given shift amount to effect a dual right or dual left shift function.
摘要翻译：用于在级联复用器移位器中移位数据的装置允许移位器以全长模式或分离模式使用，其中移位器被分成两个相等的两半，其上半部和下半场分别接收各个数据号。然后，每个数据号码同时向右移位或向左偏移给定移位量，以实现双右或双左移位功能。

6. 发明授权

US6002726A FM discriminator with automatic gain control for digital signal processors 失效
标题翻译： FM鉴频器，用于数字信号处理器的自动增益控制
公开(公告)号：US6002726A
公开(公告)日：1999-12-14
申请号：US975997
申请日：1997-11-21
申请人： Sivanand Simanapalli , Xiao-An Wang
发明人： Sivanand Simanapalli , Xiao-An Wang
IPC分类号： H03D3/00 , H04L27/14 , H04L27/08 , G06F7/52
CPC分类号： H04L27/14 , H03D3/007
摘要： A method of extracting an information bearing signal .omega.(n) from a base-band signal in the form of an inverse function with a digital signal processor. The processor includes memory and utilizes a minimum number of instructions stored in the memory. The base-band waveform comprises a plurality of complex-valued samples having respective I and Q components. The method includes the steps of receiving a first sample at an instant n having respective I(n) and Q(n) components and defining an interval for evaluating potential values for the I(n) and Q(n) components. Next, a step of transforming said I(n) and Q(n) components is performed to have respective threshold values residing in the predefined interval. Then, a step of estimating the transformed components with a series of non-inverted polynomial functions is carried out over the predefined interval. The method proceeds by extracting the information-bearing signal with the digital signal processor according to the instructions to evaluate the series of non-inverted polynomial functions.
摘要翻译：一种从数字信号处理器的反函数形式的基带信号中提取信息承载信号ω（n）的方法。处理器包括存储器并利用存储在存储器中的最少数目的指令。基带波形包括具有相应I和Q分量的多个复值样本。该方法包括以下步骤：在具有相应的I（n）和Q（n）分量的时刻n接收第一采样，并且定义用于评估I（n）和Q（n）分量的电位值的间隔。接下来，执行变换所述I（n）和Q（n）分量的步骤以具有驻留在预定间隔中的相应阈值。然后，在预定义的间隔内执行用一系列非反相多项式函数估计变换分量的步骤。该方法通过根据指令提取具有数字信号处理器的信息承载信号来评估一系列非反相多项式函数。

7. 发明授权

US5991785A Determining an extremum value and its index in an array using a dual-accumulation processor 失效
标题翻译：使用双累积处理器确定数组中的极值及其索引
公开(公告)号：US5991785A
公开(公告)日：1999-11-23
申请号：US969252
申请日：1997-11-13
申请人： Mazhar M. Alidina , Sivanand Simanapalli
发明人： Mazhar M. Alidina , Sivanand Simanapalli
IPC分类号： G06F7/544 , G06F7/02
CPC分类号： G06F7/544
摘要： A data processor determines an overall extremum value of an input set of array data, with the input set of array data partitionable into a first set of array data and a second set of array data. The data processor includes a pair of compare-select circuits implemented in an adder as well as in an arithmetic-logic unit (ALU), respectively, which operate in parallel for respectively processing the first set and the second set, and for respectively determining first and second extremum values of the first set and the second set, respectively. A first compare-select circuit of the pair of compare-select circuits determines the overall extremum value of the input set of array data from the first and second extremum values. The first compare-select circuit also determines the location of the overall extremum value in the input set of array data. The computational complexity in determining extrema is reduced by implementing compare-select features in an adder in addition to an ALU to operate in parallel to reduce the number of processing cycles.
摘要翻译：数据处理器确定阵列数据的输入集合的整体极值，其中阵列数据的输入组可分割成第一组阵列数据和第二组阵列数据。数据处理器包括分别在加法器和算术逻辑单元（ALU）中实现的一对比较选择电路，其并行操作以分别处理第一组和第二组，并分别确定第一组和第一组和第二组的第二极值。一对比较选择电路的第一比较选择电路从第一和第二极值确定阵列数据的输入集合的总极值。第一个比较选择电路还确定阵列数据的输入集合中的整体极值的位置。通过在加法器中实现比较选择特征，除了ALU以并行操作以减少处理周期数之外，减少了确定极值的计算复杂度。

8. 发明授权

US5912908A Method of efficient branch metric computation for a Viterbi convolutional decoder 失效
标题翻译：维特比卷积解码器的有效分支度量计算方法
公开(公告)号：US5912908A
公开(公告)日：1999-06-15
申请号：US976358
申请日：1997-11-21
申请人： Richard Adam Cesari , Sivanand Simanapalli
发明人： Richard Adam Cesari , Sivanand Simanapalli
IPC分类号： H03M13/23 , H03M13/41 , H04L1/00 , G06F11/10
CPC分类号： H04L1/0052 , H04L1/0054
摘要： A method of efficient branch metric computation for a Viterbi convolutional decoder wherein a reduced and optimized set of branch metrics is distributed among one or more base sets is provided. A sequence of data transformations and associations are defined according to the connections of the delay elements in the convolutional encoder to its outputs. Each encoder state is associated with one of the base sets and one of several groups of path metric equations. During the add portion of the add-compare-select phase of Viterbi decoding, a branch metric value is extracted from the base set associated with the encoder state being evaluated. The group of path metric equations associated with state being evaluated are evaluated using the extracted branch metric value. The results of the addition are then be processed according to the remaining steps of the Viterbi algorithm.
摘要翻译：提供了一种用于维特比卷积解码器的有效分支度量计算的方法，其中在一个或多个基本集合之间分布减小和优化的分支度量集合。根据卷积编码器中的延迟元件与其输出的连接来定义数据变换和关联序列。每个编码器状态与基本集合之一和路径度量方程的几组中的一个相关联。在维特比解码的加法 - 比较选择阶段的添加部分期间，从与所评估的编码器状态相关联的基本集合中提取分支量度值。使用提取的分支度量值来评估与正在评估的状态相关联的路径度量方程组。然后根据维特比算法的剩余步骤处理相加的结果。

9. 发明授权

US06801995B1 Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes 失效
标题翻译：用于对具有多个指令可选择资源类型的数字处理器的一组指令代码进行最佳编码的方法和相关联的优化的指令代码组
公开(公告)号：US06801995B1
公开(公告)日：2004-10-05
申请号：US09129116
申请日：1998-08-04
申请人： Mazhar M. Alidina , Sivanand Simanapalli , Mark E. Thierbach
发明人： Mazhar M. Alidina , Sivanand Simanapalli , Mark E. Thierbach
IPC分类号： G06F900
CPC分类号： G06F8/447 , G06F9/30145 , G06F9/30149 , G06F9/30181
摘要： A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the particular resources used, where all of the instructions in a group have one or more resource types in common. The position of the highest order active bit in the code is used to identify which resource group a particular instruction belongs to. Instructions in a resource group reserve the same number of bits to identify the specific resources to be used, and no more bits are reserved than required. The remaining unassigned bits are used to encode particular command codes. When such an encoded command is decoded, the resource group is identified by determining the highest order active bit in the instruction. This information is used to determine which bits in the instruction are command bits and which are resource-identifying bits. The specific resource information is extracted and used to select the designated resources to be used in executing the command. This encoding scheme eliminates wasted bits in instructions and thereby increases the number of instructions which can be implemented.
摘要翻译：公开了一种将唯一指令代码分配给指令集中的指令的方法。还公开了这样的编码指令集。指令根据所使用的特定资源进行分组，其中组中的所有指令都具有一个或多个共同的资源类型。代码中最高有效位的位置用于标识特定指令属于哪个资源组。资源组中的指令保留相同数量的位以标识要使用的特定资源，并且不再保留比所需的更多位。剩余的未分配位用于编码特定的命令代码。当这样的编码命令被解码时，通过确定指令中的最高有效位来识别资源组。该信息用于确定指令中哪些位是命令位，哪些是资源标识位。提取特定资源信息并用于选择在执行命令时要使用的指定资源。该编码方案消除了指令中的浪费比特，从而增加了可以实现的指令数量。

10. 发明授权

US06530014B2 Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits 失效
标题翻译：具有最小编码位的近正交双MAC指令集架构
公开(公告)号：US06530014B2
公开(公告)日：2003-03-04
申请号：US09132882
申请日：1998-08-12
申请人： Mazhar M. Alidina , Mark E. Thierbach , Sivanand Simanapalli , Larry R. Tate
发明人： Mazhar M. Alidina , Mark E. Thierbach , Sivanand Simanapalli , Larry R. Tate
IPC分类号： G06F9302
CPC分类号： G06F9/3877 , G06F7/5443 , G06F9/30101 , G06F9/30145 , G06F9/3893
摘要： A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.
摘要翻译：提供了一个近正交的双MAC指令集，其实际上只使用65个命令来实现272个命令的正交指令集的整个功能。简化指令集是通过消除相对于命令结果的对称性的指令，并且通过对诸如程序员的数据呈现顺序之类的项目施加简单的限制来实现的。命令的具体选择也由与双MAC架构相关联的双字对齐的存储器体系结构确定。简化的指令集体系结构保留了命令集的功能和固有的并行性，并且要求比完全正交集更少的命令位实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式