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1. 发明授权

US06810467B1 Method and apparatus for centralized snoop filtering 有权
标题翻译：用于集中侦听过滤的方法和装置
公开(公告)号：US06810467B1
公开(公告)日：2004-10-26
申请号：US09643382
申请日：2000-08-21
申请人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
发明人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0822 , G06F12/0828 , G06F2212/507
摘要： An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the system's nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.
摘要翻译：利用中央窥探滤波器的计算机系统的示例性实施例包括经由交换设备耦合在一起的多个节点。每个节点可以包括几个处理器和高速缓存以及系统存储器块。从一个节点到另一个节点的所有业务通过交换设备进行。交换设备包括一个窥探过滤器，其跟踪计算机系统中所有高速缓存的高速缓存行一致性信息。监听过滤器具有足够的条目来跟踪所有系统节点中所有高速缓存中所有条目的标签和状态信息。除了标签和状态信息之外，窥探过滤器存储指示哪个节点具有每个高速缓存行的副本的信息。窥探过滤器部分地用于在不包含主体高速缓存行的副本的节点处执行窥探事务，从而减少系统开销，减少跨系统互连总线的流量，并减少执行窥探所需的时间量交易。

2. 发明授权

US07996625B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07996625B2
公开(公告)日：2011-08-09
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

3. 发明授权

US07234029B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07234029B2
公开(公告)日：2007-06-19
申请号：US09749660
申请日：2000-12-28
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

4. 发明授权

US07093079B2 Snoop filter bypass 有权
标题翻译：窥探过滤器旁路
公开(公告)号：US07093079B2
公开(公告)日：2006-08-15
申请号：US10323200
申请日：2002-12-17
申请人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
发明人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082
摘要： Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.
摘要翻译：描述了用于处理包括多个高速缓存节点的计算设备的相干请求的机器可读介质，方法和装置。在一些实施例中，相干开关可以从请求的高速缓存节点接收对一行存储器的相干请求。基于是否启用窥探过滤器旁路模式，相干交换机可以进一步向一个或多个非请求高速缓存节点发出窥探请求。特别地，当不在窥探过滤器旁路模式时，相干开关可以从窥探过滤器获得一致性数据，并且可以基于从窥探过滤器获得的一致性数据向0个或更多个非请求缓存节点发出窥探请求。此外，在窥探过滤器旁路模式中的相干交换机可以绕过窥探过滤器并且可以向所有不请求的缓存代理发出窥探请求。

5. 发明授权

US07383398B2 Preselecting E/M line replacement technique for a snoop filter 有权
标题翻译：为窥探过滤器预选E / M线更换技术
公开(公告)号：US07383398B2
公开(公告)日：2008-06-03
申请号：US11394503
申请日：2006-03-31
申请人： Lily P Looi , Liqun Cheng , Kai Cheng , Faye A Briggs
发明人： Lily P Looi , Liqun Cheng , Kai Cheng , Faye A Briggs
IPC分类号： G06F12/12
CPC分类号： G06F12/082 , G06F12/0831 , G06F12/121
摘要： A snoop filter maintains data coherency information for multiple caches in a multi-processor system. When a new request for a memory line arrives, an entry of the snoop filter is selected for replacement if there is no available slot in the snoop filter to accommodate the new request. The selected entry is among the entries predicted to be short-lived based on a coherency state. An invalidation message is sent to the one of the caches with which the selected entry is associated.
摘要翻译：监听过滤器在多处理器系统中维护多个高速缓存的数据一致性信息。当存储线路的新请求到达时，如果窥探过滤器中没有可用的插槽以容纳新的请求，则选择窥探过滤器的条目进行替换。所选条目是基于一致性状态预测为短命的条目之一。将无效消息发送到与所选条目关联的缓存中的一个缓存。

6. 发明申请

US20070204111A1 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
公开(公告)号：US20070204111A1
公开(公告)日：2007-08-30
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye Briggs , Akhilesh Kumar , Lily Looi , Kai Cheng
发明人： Manoj Khare , Faye Briggs , Akhilesh Kumar , Lily Looi , Kai Cheng
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

7. 发明授权

US09600416B2 Apparatus and method for implementing a multi-level memory hierarchy 有权
公开(公告)号：US09600416B2
公开(公告)日：2017-03-21
申请号：US13997189
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
IPC分类号： G06F13/12 , G06F13/38 , G06F12/08 , G11C11/406 , G11C14/00
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897 , G06F2212/2024 , G06F2212/205 , G11C11/40615 , G11C14/009 , Y02D10/13
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

8. 发明授权

US08487316B2 Method of manufacturing an integrated semiconductor substrate structure with device areas for definition of GaN-based devices and CMOS devices 有权
标题翻译：制造具有用于GaN基器件和CMOS器件的定义的器件区域的集成半导体衬底结构的方法
公开(公告)号：US08487316B2
公开(公告)日：2013-07-16
申请号：US12914930
申请日：2010-10-28
申请人： Kai Cheng , Stefan Degroote
发明人： Kai Cheng , Stefan Degroote
IPC分类号： H01L29/04 , H01L29/15 , H01L31/036
CPC分类号： H01L27/0605 , H01L21/8252 , H01L21/8258
摘要： An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.
摘要翻译：公开了一种集成半导体衬底结构。一方面，该结构包括衬底，GaN异质结构和半导体衬底层。 GaN异质结构存在于用于GaN基器件的定义的第一器件区域中，并且至少部分地被保护层覆盖。半导体衬底层存在于用于CMOS器件定义的第二器件区域中。至少GaN基异质结构和半导体衬底层中的至少一个设置在衬底中的至少一个沟槽中，使得GaN异质结构和半导体衬底层横向并置。

9. 发明授权

US08433856B2 Pseudo least recently used replacement/allocation scheme in request agent affinitive set-associative snoop filter 有权
公开(公告)号：US08433856B2
公开(公告)日：2013-04-30
申请号：US12558796
申请日：2009-09-14
申请人： Kai Cheng , David C. Lee , John A. Urbanski
发明人： Kai Cheng , David C. Lee , John A. Urbanski
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/0822 , G06F12/123
摘要： The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

10. 发明授权

US08429367B2 Systems, methods and apparatuses for clock enable (CKE) coordination 有权
标题翻译：用于时钟使能（CKE）协调的系统，方法和装置
公开(公告)号：US08429367B2
公开(公告)日：2013-04-23
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/225
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。描述和要求保护其他实施例。

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