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1. 发明授权

US07093079B2 Snoop filter bypass 有权
标题翻译：窥探过滤器旁路
公开(公告)号：US07093079B2
公开(公告)日：2006-08-15
申请号：US10323200
申请日：2002-12-17
申请人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
发明人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082
摘要： Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.
摘要翻译：描述了用于处理包括多个高速缓存节点的计算设备的相干请求的机器可读介质，方法和装置。在一些实施例中，相干开关可以从请求的高速缓存节点接收对一行存储器的相干请求。基于是否启用窥探过滤器旁路模式，相干交换机可以进一步向一个或多个非请求高速缓存节点发出窥探请求。特别地，当不在窥探过滤器旁路模式时，相干开关可以从窥探过滤器获得一致性数据，并且可以基于从窥探过滤器获得的一致性数据向0个或更多个非请求缓存节点发出窥探请求。此外，在窥探过滤器旁路模式中的相干交换机可以绕过窥探过滤器并且可以向所有不请求的缓存代理发出窥探请求。

2. 发明授权

US07617329B2 Programmable protocol to support coherent and non-coherent transactions in a multinode system 有权
标题翻译：可编程协议支持多节点系统中的相干和非相干事务
公开(公告)号：US07617329B2
公开(公告)日：2009-11-10
申请号：US10335001
申请日：2002-12-30
申请人： Tuan M. Quach , Lily P. Looi , Kai Cheng
发明人： Tuan M. Quach , Lily P. Looi , Kai Cheng
IPC分类号： G06F15/16
CPC分类号： G06F15/17375 , G06F12/0831
摘要： A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol distributed (SPPD). A snoop filter in the SPS tracks which nodes may be using various memory addresses. A scalability port protocol central (SPPC) is responsible for processing messages to support coherent and non-coherent transactions in the system.
摘要翻译：系统包括可扩展性端口交换机（SPS）和多个节点。 SPS具有多个端口，每个端口耦合到一个节点。每个端口连接到可扩展端口协议分发（SPPD）。 SPS中的监听滤波器跟踪哪些节点可能使用各种存储器地址。可扩展性端口协议中心（SPPC）负责处理消息以支持系统中的一致和非一致性事务。

3. 发明授权

US08787110B2 Realignment of command slots after clock stop exit 有权
标题翻译：在时钟停止退出后重新调整命令槽
公开(公告)号：US08787110B2
公开(公告)日：2014-07-22
申请号：US13537688
申请日：2012-06-29
申请人： Tuan M. Quach , Victor V. Tran
发明人： Tuan M. Quach , Victor V. Tran
IPC分类号： G11C8/00
CPC分类号： G11C11/4096 , G11C5/066 , G11C7/1057 , G11C7/1063 , G11C7/1069 , G11C7/1084 , G11C7/109 , G11C7/1096 , G11C7/222 , G11C11/4076
摘要： Described herein are embodiments of dynamic command slot realignment after clock stop exit. An apparatus configured for dynamic command slot realignment after clock stop exit may include memory including a first memory module configured to receive commands over a first channel via a first command slot and a second memory module configured to receive commands over a second channel via a second command slot, and a memory buffer configured to receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot. Other embodiments may be described and/or claimed.
摘要翻译：这里描述了时钟停止退出之后的动态命令槽重新对准的实施例。配置用于在时钟停止退出之后用于动态命令时隙重新对准的装置可以包括存储器，其包括被配置为经由第一命令时隙在第一信道上接收命令的第一存储器模块和经配置以经由第二命令在第二信道上接收命令的第二存储器模块槽和存储器缓冲器，其被配置为接收针对第一命令时隙的时钟同步命令，并且响应于检测到第二命令时隙中的时钟同步命令来执行写指针交换，以重新对准第一命令时隙和第二命令时隙。可以描述和/或要求保护其他实施例。

4. 发明授权

US06754754B1 Apparatus and method for end of interrupt handling 有权
标题翻译：中断处理结束的装置和方法
公开(公告)号：US06754754B1
公开(公告)日：2004-06-22
申请号：US09475485
申请日：1999-12-30
申请人： Tuan M. Quach , Subbarao S. Vanka
发明人： Tuan M. Quach , Subbarao S. Vanka
IPC分类号： G06F948
CPC分类号： G06F13/24
摘要： An interrupt vector is issued by an interrupt controller in response to an interrupt request. A processor executes an interrupt service routine in response to receiving the interrupt vector. Upon the completion of the interrupt service routine, the processor issues an end of interrupt vector to the interrupt controller. The interrupt controller substantially simultaneously compares the end of interrupt vector with a plurality of stored interrupt vectors.
摘要翻译：中断控制器响应中断请求发出中断向量。响应于接收到中断向量，处理器执行中断服务程序。中断服务程序完成后，处理器向中断控制器发出中断向量的结束。中断控制器基本上同时将中断向量的结束与多个存储的中断向量进行比较。

5. 发明授权

US07054974B2 System for end of interrupt handling 有权
标题翻译：中断处理结束的系统
公开(公告)号：US07054974B2
公开(公告)日：2006-05-30
申请号：US10839857
申请日：2004-05-05
申请人： Tuan M. Quach , Subbarao S. Vanka
发明人： Tuan M. Quach , Subbarao S. Vanka
IPC分类号： G06F9/48 , G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector with a plurality of interrupts.
摘要翻译：中断控制器包括处理中断（EOI）向量的至少一端的电路，该电路能够基本上同时将至少一个EOI向量与多个中断进行比较。

6. 发明授权

US07219167B2 Accessing configuration registers by automatically changing an index 有权
标题翻译：通过自动更改索引来访问配置寄存器
公开(公告)号：US07219167B2
公开(公告)日：2007-05-15
申请号：US10671973
申请日：2003-09-25
申请人： Tuan M. Quach , Reza E. Daftari
发明人： Tuan M. Quach , Reza E. Daftari
IPC分类号： G06F3/00 , G06F9/00
CPC分类号： G06F9/4411
摘要： An embodiment of the invention is directed to a method for accessing configuration registers. An indication that an attempt has been made to access a first register is received. This first register reflects an index variable that points to a configuration register. Next, an indication that an attempt has been made to access a second register is received. This second register reflects part of the contents of a configuration register to which the index variable points. Next, without waiting for another attempt to access the first register, the index variable is changed to point to another configuration register. Other embodiments are also described and claimed.
摘要翻译：本发明的实施例涉及用于访问配置寄存器的方法。接收到尝试访问第一寄存器的指示。该第一个寄存器反映指向一个配置寄存器的索引变量。接下来，接收到尝试访问第二寄存器的指示。该第二个寄存器反映了索引变量指向的配置寄存器的一部分内容。接下来，在不等待另一次尝试访问第一个寄存器的情况下，索引变量被更改为指向另一个配置寄存器。还描述和要求保护其他实施例。

7. 发明申请

US20160092353A1 ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY 审中-公开
标题翻译：从老化记忆建立冷藏库
公开(公告)号：US20160092353A1
公开(公告)日：2016-03-31
申请号：US14496773
申请日：2014-09-25
申请人： Robert C. Swanson , Robert W. Cone , Brian R. Bennett , Vladimir Matveyenko , Paul D. Herring , Jordan A. Horwich , Tuan M. Quach , Cuong D. Dinh , Paul M. Leung , Luis E. Valdez , Joseph Hamann , Russell A. Hamann , Michael P. Pham , Caleb C. Molitoris , Kervin T. Ngo , Cory Li , Ola Fadiran , Jason R. Ng , Richard I. Guerin , Jay H. Danver , Chris Kun K. Cheung , Satish R. Natla , Rodel I. Cruz-Herrera
发明人： Robert C. Swanson , Robert W. Cone , Brian R. Bennett , Vladimir Matveyenko , Paul D. Herring , Jordan A. Horwich , Tuan M. Quach , Cuong D. Dinh , Paul M. Leung , Luis E. Valdez , Joseph Hamann , Russell A. Hamann , Michael P. Pham , Caleb C. Molitoris , Kervin T. Ngo , Cory Li , Ola Fadiran , Jason R. Ng , Richard I. Guerin , Jay H. Danver , Chris Kun K. Cheung , Satish R. Natla , Rodel I. Cruz-Herrera
IPC分类号： G06F12/06 , G06F12/12 , G06F11/30
CPC分类号： G11C29/765 , G06F11/3037 , G06F11/3055 , G06F12/0238 , G06F2201/88 , G06F2212/7202 , G06F2212/7203 , G06F2212/7206
摘要： Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.
摘要翻译：系统和方法可以提供用于检测针对目标存储器区域的待决写入操作，并且确定目标存储器区域是否满足等待写入操作的退化条件。此外，如果目标存储器区域满足劣化条件，则可以将目标存储器区域自动重新配置为冷存储区域。在一个示例中，确定目标存储器区域是否满足劣化条件包括基于挂起的写入操作来更新针对目标存储器区域的写入操作的数量，并将写入操作的数量与偏移值进行比较，其中劣化条件是如果写操作的数量超过偏移值，则满足。

8. 发明申请

US20140003184A1 REALIGNMENT OF COMMAND SLOTS AFTER CLOCK STOP EXIT 有权
标题翻译：时钟停止退出之后的命令缓存的实现
公开(公告)号：US20140003184A1
公开(公告)日：2014-01-02
申请号：US13537688
申请日：2012-06-29
申请人： Tuan M. Quach , Victor V. Tran
发明人： Tuan M. Quach , Victor V. Tran
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C11/4096 , G11C5/066 , G11C7/1057 , G11C7/1063 , G11C7/1069 , G11C7/1084 , G11C7/109 , G11C7/1096 , G11C7/222 , G11C11/4076
摘要： Described herein are embodiments of dynamic command slot realignment after clock stop exit. An apparatus configured for dynamic command slot realignment after clock stop exit may include memory including a first memory module configured to receive commands over a first channel via a first command slot and a second memory module configured to receive commands over a second channel via a second command slot, and a memory buffer configured to receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot. Other embodiments may be described and/or claimed.
摘要翻译：这里描述了时钟停止退出之后的动态命令槽重新对准的实施例。配置用于在时钟停止退出之后用于动态命令时隙重新对准的装置可以包括存储器，其包括被配置为经由第一命令时隙在第一信道上接收命令的第一存储器模块和经配置以经由第二命令在第二信道上接收命令的第二存储器模块插槽和配置成接收针对第一命令时隙的时钟同步命令的存储器缓冲器，并且响应于检测到第二命令时隙中的时钟同步命令来执行写指针交换，以重新对准第一命令时隙和第二命令时隙。可以描述和/或要求保护其他实施例。

9. 发明授权

US07308510B2 Method and apparatus for avoiding live-lock in a multinode system 有权
标题翻译：用于避免多节点系统中实时锁定的方法和装置
公开(公告)号：US07308510B2
公开(公告)日：2007-12-11
申请号：US10431871
申请日：2003-05-07
申请人： Tuan M. Quach
发明人： Tuan M. Quach
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F9/524
摘要： A reordering priority to grant higher priority for a request over a response when a predetermined condition is detected for live-lock prevention is discussed. Specifically. A a circuit and flowchart for preventing a live lock situation is discussed without a need for a bus converter. In one example, a detection of a PRETRY response in a response queue is analyzed.
摘要翻译：讨论了当检测到用于实时锁定预防的预定条件时，重新排序优先级以对响应的请求授予较高优先级。特别。讨论了用于防止活锁的情况的电路和流程图，而不需要总线转换器。在一个示例中，分析响应队列中的PRETRY响应的检测。

10. 发明授权

US08842490B2 Apparatus and method for selectively using a memory command clock as a reference clock 有权
标题翻译：用于选择性地使用存储器命令时钟作为参考时钟的装置和方法
公开(公告)号：US08842490B2
公开(公告)日：2014-09-23
申请号：US13537696
申请日：2012-06-29
申请人： Tuan M. Quach , Cuong D. Dinh
发明人： Tuan M. Quach , Cuong D. Dinh
IPC分类号： G11C8/00
CPC分类号： G11C7/1084 , G11C7/1057 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： Described herein are embodiments of selectively setting a memory command clock as a memory buffer reference clock. An apparatus configured for setting a memory command clock as a memory buffer reference clock may include a memory buffer configured to interface between a host and memory, and reference clock selection logic configured to selectively set a memory command clock as a memory buffer reference clock. Other embodiments may be described and/or claimed.
摘要翻译：这里描述了选择性地将存储器命令时钟设置为存储器缓冲器参考时钟的实施例。配置用于将存储器命令时钟设置为存储器缓冲器参考时钟的装置可以包括被配置为在主机和存储器之间进行接口的存储器缓冲器和被配置为选择性地将存储器命令时钟设置为存储器缓冲器参考时钟的参考时钟选择逻辑。可以描述和/或要求保护其他实施例。

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