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    • 1. 发明授权
    • Methods of forming a floating junction on a solar cell with a particle masking layer
    • 在具有颗粒掩蔽层的太阳能电池上形成浮点的方法
    • US08513104B2
    • 2013-08-20
    • US13172040
    • 2011-06-29
    • Malcolm AbbottMaxim KelmanEric RosenfeldElena RogojinaGiuseppe Scardera
    • Malcolm AbbottMaxim KelmanEric RosenfeldElena RogojinaGiuseppe Scardera
    • H01L21/22H01L21/38
    • H01L21/2255H01L31/022425H01L31/068H01L31/1804Y02E10/547Y02P70/521
    • A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns. The method also includes exposing the substrate to a set of etchants for a third time period, wherein the front surface PSG layer and the rear surface PSG layer are substantially removed; depositing a front surface SiNx layer and a rear surface SiNx layer; and forming a rear metal contact on the rear surface through the rear surface SiNx layer proximate to the set of patterns.
    • 公开了一种在衬底上形成浮点的方法。 该方法包括提供掺杂有硼原子的衬底,该衬底包括前表面和后表面。 该方法还包括在一组图案中的后表面上沉积一组掩模颗粒; 以及在烘烤环境中将基底加热到第一温度并且持续第一时间段以便产生颗粒掩蔽层。 该方法还包括在第二温度和第二时间段内将衬底暴露于磷沉积环境中,其中形成前表面PSG层,前表面磷扩散层,后表面PSG层和后表面磷扩散层 ,并且其中靠近所述图案集合的所述衬底中的第一磷掺杂剂表面浓度小于所述衬底中不接近所述图案集合的第二掺杂剂表面浓度。 该方法还包括将衬底暴露于一组第三时间的蚀刻剂,其中基本上去除了前表面PSG层和后表面PSG层; 沉积前表面SiNx层和后表面SiNx层; 以及通过靠近所述一组图案的后表面SiNx层在后表面上形成后金属接触。
    • 4. 发明授权
    • Single platform electronic tester
    • 单平台电子测试仪
    • US07191368B1
    • 2007-03-13
    • US09938157
    • 2001-08-22
    • Donald V. OrganKenneth J. LanierRoger W. BlethenH. Neil KellyMichael G. DavisJeffrey H. PerkinsTommie BerryPhillip BurlisonMark DeomeChristopher J. HannafordEdward J. TerrenziDavid MenisDavid W. CurryEric Rosenfeld
    • Donald V. OrganKenneth J. LanierRoger W. BlethenH. Neil KellyMichael G. DavisJeffrey H. PerkinsTommie BerryPhillip BurlisonMark DeomeChristopher J. HannafordEdward J. TerrenziDavid MenisDavid W. CurryEric Rosenfeld
    • G06F11/00
    • G01R1/025G01R31/2834G01R31/319
    • An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
    • 一个电子测试仪,在单个平台上具有数字,模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路,混合信号集成电路,数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件,并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件,并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将内存测试模式应用到与测试头耦合的待测器件,并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字,模拟和存储器测试电路到被测器件的数字,模拟和存储器测试信号的应用,使得施加到被测器件的信号可以是单独的数字测试信号,只有模拟测试信号 ,单独记忆测试信号,或混合数字,模拟和存储器测试信号。 测试头,数字测试电路,模拟测试电路,存储器测试电路和计算机可操作为单个平台。
    • 5. 发明申请
    • Method For Providing Electronic Medical Records
    • 提供电子病历的方法
    • US20080172254A1
    • 2008-07-17
    • US12014281
    • 2008-01-15
    • Eric RosenfeldMilton Hauser
    • Eric RosenfeldMilton Hauser
    • G06Q50/00
    • G06Q50/22G06Q10/10G06Q50/24
    • A system and method for collecting, aggregating and providing electronic medical records is presented. A patient enters information regarding medical services providers to a medical records service as part of a digital medical profile. The patient further submits a records authorization authorizing the release of the patient's medical records to the medical records service. Health care records are requested from each of the patient's medical services providers, and upon receipt, entered into a database. An interactive healthcare calendar permits a patient to enter medical appointments. Updates to the medical records are requested from relevant medical services providers at regular intervals, or after an appointment in the interactive healthcare calendar. The stored medical records are transferred to a portable records storage device such as a USB key, which may be carried by the patient for use by medical services providers, or in the case emergency medical treatment is needed.
    • 介绍了收集,汇总和提供电子病历的系统和方法。 患者将有关医疗服务提供者的信息输入医疗记录服务,作为数字医疗档案的一部分。 患者进一步提交记录授权,授权向病历服务发放病人的病历。 每个病人的医疗服务提供者都要求提供医疗保健记录,并在收到后输入数据库。 互动医疗日历允许患者进入医疗约会。 定期向有关医疗服务提供者请求医疗记录的更新,或在交互式医疗日历中预约之后。 存储的医疗记录被传送到便携式记录存储装置,例如USB密钥,其可以由患者携带以供医疗服务提供商使用,或者在需要紧急医疗的情况下。
    • 10. 发明授权
    • Single platform electronic tester
    • 单平台电子测试仪
    • US06675339B1
    • 2004-01-06
    • US09935453
    • 2001-08-22
    • Kenneth J. LanierRoger W. BlethenH. Neil KellyMichael G. DavisJeffrey H. PerkinsTommie BerryPhillip BurlisonMark DeomeChristopher J. HannafordEdward J. TerrenziDavid MenisDavid W. CurryEric Rosenfeld
    • Kenneth J. LanierRoger W. BlethenH. Neil KellyMichael G. DavisJeffrey H. PerkinsTommie BerryPhillip BurlisonMark DeomeChristopher J. HannafordEdward J. TerrenziDavid MenisDavid W. CurryEric Rosenfeld
    • G01R3128
    • G01R1/025G01R31/2834G01R31/319
    • An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
    • 一个电子测试仪,在单个平台上具有数字,模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路,混合信号集成电路,数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件,并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件,并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将存储器测试图案应用于被测器件,耦合到测试头,并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字,模拟和存储器测试电路到被测器件的数字,模拟和存储器测试信号的应用,使得施加到被测器件的信号可以是单独的数字测试信号,只有模拟测试信号 ,单独记忆测试信号,或混合数字,模拟和存储器测试信号。 测试头,数字测试电路,模拟测试电路,存储器测试电路和计算机可操作为单个平台。