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1. 发明授权

US07191368B1 Single platform electronic tester 失效
标题翻译：单平台电子测试仪
公开(公告)号：US07191368B1
公开(公告)日：2007-03-13
申请号：US09938157
申请日：2001-08-22
申请人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G06F11/00
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译：一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。测试头耦合到被测设备。被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号，单独记忆测试信号，或混合数字，模拟和存储器测试信号。测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

2. 发明授权

US06449741B1 Single platform electronic tester 有权
标题翻译：单平台电子测试仪
公开(公告)号：US06449741B1
公开(公告)日：2002-09-10
申请号：US09183038
申请日：1998-10-30
申请人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： H02H305
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译：一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。测试头耦合到被测设备。被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号，单独记忆测试信号，或混合数字，模拟和存储器测试信号。测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

3. 发明授权

US06675339B1 Single platform electronic tester 有权
标题翻译：单平台电子测试仪
公开(公告)号：US06675339B1
公开(公告)日：2004-01-06
申请号：US09935453
申请日：2001-08-22
申请人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G01R3128
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译：一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。测试头耦合到被测设备。被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。存储器测试电路将存储器测试图案应用于被测器件，耦合到测试头，并响应于存储器测试模式接收来自被测器件的存储器输出。测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号，单独记忆测试信号，或混合数字，模拟和存储器测试信号。测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

4. 发明授权

US07092837B1 Single platform electronic tester 有权
公开(公告)号：US07092837B1
公开(公告)日：2006-08-15
申请号：US10663469
申请日：2003-09-15
申请人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G06F1/06
CPC分类号： G01R31/31903 , G11C29/56 , G11C2029/5602
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

5. 发明授权

US06512989B1 Generating and controlling analog and digital signals on a mixed signal test system 失效
标题翻译：在混合信号测试系统上生成和控制模拟和数字信号
公开(公告)号：US06512989B1
公开(公告)日：2003-01-28
申请号：US09276849
申请日：1999-03-26
申请人： Mark Deome , Donald V. Organ
发明人： Mark Deome , Donald V. Organ
IPC分类号： G06F1900
CPC分类号： G01R31/31917 , G01R31/3167
摘要： An automated test system that has analog and digital resources for testing mixed signal ICs. A control pattern is provided that is used by the automated test system to simultaneously control both the digital resources and the analog resources. The control pattern is comprised of a sequentially executed two-dimensional array with columns corresponding to analog and digital resources. The automated test system uses the control pattern to control both the analog and digital resources.
摘要翻译：具有用于测试混合信号IC的模拟和数字资源的自动化测试系统。提供了一种由自动测试系统用于同时控制数字资源和模拟资源的控制模式。控制模式由具有对应于模拟和数字资源的列的顺序执行的二维阵列组成。自动测试系统使用控制模式来控制模拟和数字资源。

6. 发明授权

US07512857B1 Pattern correction circuit 失效
标题翻译：图案校正电路
公开(公告)号：US07512857B1
公开(公告)日：2009-03-31
申请号：US11193873
申请日：2005-07-29
申请人： Warren Necoechea , Timothy Alton , Mark Deome , Henk Zantman
发明人： Warren Necoechea , Timothy Alton , Mark Deome , Henk Zantman
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G01R31/318307 , G01R31/318371
摘要： A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.
摘要翻译：描述了一种在电子测试仪中利用利用XOR数据格式化的第一图案的方法。该方法包括将第一图案划分成至少第一组和第二组，测试器连续地执行第一组和第二组。该方法还包括假设如果第一组的结束状态不等于假定的进入状态，则每个组的进入状态是两个二进制条件之一，并且针对第二组反转编程的命令。

7. 发明授权

US06563298B1 Separating device response signals from composite signals 有权
标题翻译：从复合信号中分离设备响应信号
公开(公告)号：US06563298B1
公开(公告)日：2003-05-13
申请号：US09639517
申请日：2000-08-15
申请人： William R. Creek , Mark Deome , R. Warren Necoechea
发明人： William R. Creek , Mark Deome , R. Warren Necoechea
IPC分类号： G01R3126
CPC分类号： G01R31/318544
摘要： An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.
摘要翻译：一种用于接收从被测设备发送的响应信号的装置。该装置包括用于识别包含在复合信号中的响应信号的引脚电子装置。复合信号是响应信号和测试信号的复合或或和。引脚电子设备具有将测试信号发送到被测器件的驱动器，以及用于接收复合信号并从复合信号中分离响应信号的接收器。

8. 发明授权

US06768960B2 System for and method of performing device-oriented tests 失效
标题翻译：执行面向设备的测试的系统和方法
公开(公告)号：US06768960B2
公开(公告)日：2004-07-27
申请号：US09863178
申请日：2001-05-23
申请人： Don Organ , Mark Deome , Jeff Perkins , Bob Quinn , Juliekara Techasaratoole
发明人： Don Organ , Mark Deome , Jeff Perkins , Bob Quinn , Juliekara Techasaratoole
IPC分类号： G06F1900
CPC分类号： G01R31/31926
摘要： A method of connecting one or more testing devices to ports of a DUT through a switching network, to execute a testing procedure includes generating a switching network map defining connections within the switching network to implement electrical paths through the switching network. Each of the electrical paths is representative of a connection of one of the testing devices to one of the I/O ports of the DUT. The method further includes receiving commands that uniquely specify an electrical path connecting a particular testing device to a particular I/O port of the DUT. The method compares each command to the switching network map to identify a corresponding electrical path through the switching network, and implements that path associated the command through the network. The method further includes sequentially implementing the electrical paths corresponding to the one or more commands in a predetermined order.
摘要翻译：通过交换网络将一个或多个测试设备连接到DUT的端口的方法，以执行测试过程包括生成定义交换网络内的连接以实现通过交换网络的电路径的交换网络图。每个电路径代表了一个测试设备与被测设备的一个I / O端口的连接。该方法还包括接收唯一指定将特定测试设备连接到DUT的特定I / O端口的电路径的命令。该方法将每个命令与交换网络映射进行比较，以识别通过交换网络的相应电气路径，并通过网络实现与该命令相关联的路径。该方法还包括以预定顺序顺序地实现与一个或多个命令相对应的电路径。

9. 发明授权

US06703825B1 Separating device response signals from composite signals 失效
标题翻译：从复合信号中分离设备响应信号
公开(公告)号：US06703825B1
公开(公告)日：2004-03-09
申请号：US10356172
申请日：2003-01-31
申请人： William R. Creek , Mark Deome , R. Warren Necoechea
发明人： William R. Creek , Mark Deome , R. Warren Necoechea
IPC分类号： G01R3128
CPC分类号： G01R31/318544
摘要： An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.
摘要翻译：一种用于接收从被测设备发送的响应信号的装置。该装置包括用于识别包含在复合信号中的响应信号的引脚电子装置。复合信号是响应信号和测试信号的复合或或和。引脚电子设备具有将测试信号发送到被测器件的驱动器，以及用于接收复合信号并从复合信号中分离响应信号的接收器。

10. 发明授权

US06560756B1 Method and apparatus for distributed test pattern decompression 失效
标题翻译：分布式测试模式解压缩的方法和装置
公开(公告)号：US06560756B1
公开(公告)日：2003-05-06
申请号：US09898160
申请日：2001-07-02
申请人： R. Warren Necoechea , Mark Deome , Dave Hollinbeck
发明人： R. Warren Necoechea , Mark Deome , Dave Hollinbeck
IPC分类号： G06F1750
CPC分类号： G01R31/31921
摘要： A method is described that decompresses at least a section of a first test pattern within a first decompression engine while simultaneously decompressing at least a section of a second test pattern within a second decompression engine. The first test pattern is to be applied to a first device under test (DUT) connection. The second test pattern is to be applied to a second DUT connection.
摘要翻译：描述了一种方法，其在第一解压缩引擎内解压缩第一测试模式的至少一部分，同时对第二解压缩引擎内的第二测试模式的至少一部分进行解压缩。第一个测试模式应用于第一个受测设备（DUT）连接。第二个测试模式应用于第二个DUT连接。

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