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1. 发明授权

US5253197A Semiconductor associative memory device with current sensing 失效
标题翻译：具有电流检测的半导体联想存储器件
公开(公告)号：US5253197A
公开(公告)日：1993-10-12
申请号：US580464
申请日：1990-09-11
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04
CPC分类号： G11C15/04 , G06F12/0895 , G06F12/1054 , Y02B60/1225
摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
摘要翻译：在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成电压信息。在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测能力也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

2. 发明授权

US5107141A BiCMOS logic circuit using 0.5 micron technology and having an operating potential difference of less than 4 volts 失效
标题翻译： BiCMOS逻辑电路采用0.5微米技术，工作电位差小于4伏特
公开(公告)号：US5107141A
公开(公告)日：1992-04-21
申请号：US604454
申请日：1990-10-29
申请人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0944
CPC分类号： H03K19/0013 , H03K19/0136 , H03K19/09448
摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.
摘要翻译：适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

3. 发明授权

US5218567A Match detection circuit for cache memory apparatus 失效
标题翻译：高速缓冲存储器装置的匹配检测电路
公开(公告)号：US5218567A
公开(公告)日：1993-06-08
申请号：US789003
申请日：1991-11-07
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04
CPC分类号： G06F12/1054 , G06F12/0895 , G11C15/04
摘要： A cache memory apparatus made up of a memory cell array (300) and a match detection circuit is disclosed. The match detection circuit produces a detection signal related to whether a search data coincides with a data read out of the memory cell array (300). The match detection circuit applies complementary signals (d, d) of the data read from the memory cell array (300) to the bases of bipolar differential transistors (10, 11), the gates of a pair of field effect transistors (16, 17) are supplied with complementary signals (a, a) of the search data, and the bases of a pair of emitter-follower transistors (12, 13) are connected to the collectors of the bipolar differential transistors (10, 11), thereby producing a detection signal (HITO) from the jointly-connected emitters thereof.
摘要翻译：公开了一种由存储单元阵列（300）和匹配检测电路构成的高速缓存存储装置。匹配检测电路产生与搜索数据是否与从存储单元阵列（300）读出的数据一致的检测信号。匹配检测电路将从存储单元阵列（300）读取的数据的互补信号（d，＆amp; upbar＆d）施加到双极差分晶体管（10,11）的基极，一对场效应晶体管（16， 17）被提供有搜索数据的互补信号（a，＆amp; upbar＆a），并且一对射极跟随器晶体管（12,13）的基极连接到双极差分晶体管（10,11）的集电极，从而从其共同连接的发射器产生检测信号（＆amp; upbar＆amp; H）。

4. 发明授权

US4928265A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4928265A
公开(公告)日：1990-05-22
申请号：US266148
申请日：1988-11-02
申请人： Hisayuki Higuchi , Noriyuki Homma , Makoto Suzuki , Suguru Tachibana
发明人： Hisayuki Higuchi , Noriyuki Homma , Makoto Suzuki , Suguru Tachibana
IPC分类号： G11C11/416
CPC分类号： G11C11/416
摘要： Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.
摘要翻译：考虑到半导体存储器的访问时间的偏差，至少第一和第二存储器电路连接到读出放大器的输出。读出放大器的输出是以不同的定时交替地输入到这两个存储器电路。存储在这些存储器电路中的数据被交替地传送到数据输出电路。即使当访问时间变长时，可以在由时钟周期确定的短时间间隔内从数据输出电路的输出端连续地读出期望的感测数据。当访问时间变短时，即使在将第一存储器电路中的第一数据传送到数据输出电路的定时从读出放大器的输出产生第二数据时，保持在第一存储器电路中的第一数据为防止第二个数据被更新。在这种情况下，也可以在由时钟周期确定的时间间隔内从数据输出电路的输出端连续读出期望的检测数据。

5. 发明授权

US06342710B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06342710B1
公开(公告)日：2002-01-29
申请号：US09521957
申请日：2000-03-09
申请人： Hisayuki Higuchi , Suguru Tachibana , Koichiro Ishibashi , Keijiro Uehara
发明人： Hisayuki Higuchi , Suguru Tachibana , Koichiro Ishibashi , Keijiro Uehara
IPC分类号： H01L2976
CPC分类号： G11C11/5621 , G11C15/04
摘要： A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.
摘要翻译：一种半导体集成电路，特别是用于安装在微处理器LSI中的用于高速低功耗表格旁路缓冲器的电路。半导体集成电路设置有用于将输入的多位数据信号与存储的数据进行比较的场效应晶体管和至少在数据信号与存储的数据进行比较时施加电流的符合检测信号线（25）。当数据信号与存储的数据一致时，晶体管（26）导通。晶体管（26）的数量等于输入的数据信号的数量。晶体管的漏极（260）并联连接，源极并联连接并以预定电压供电，通过集成电路，通过检测电位来检测输入的数据信号是否与存储的数据一致的一致检测信号线（25）。

6. 发明授权

US6121646A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US6121646A
公开(公告)日：2000-09-19
申请号：US913407
申请日：1997-12-05
申请人： Hisayuki Higuchi , Suguru Tachibana , Koichiro Ishibashi , Keijiro Uehara
发明人： Hisayuki Higuchi , Suguru Tachibana , Koichiro Ishibashi , Keijiro Uehara
IPC分类号： G11C11/56 , G11C15/04 , H01L29/76
CPC分类号： G11C11/5621 , G11C15/04
摘要： A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.
摘要翻译： PCT No.PCT / JP96 / 00701 Sec。 371 1997年12月5日第 102（e）日期1997年12月5日PCT 1996年3月18日PCT公布。出版物WO96 / 29705 日期1996年9月26日一种半导体集成电路，特别是用于安装在微处理器LSI中的高速低功耗表格旁路缓冲器的电路。半导体集成电路设置有用于将输入的多位数据信号与存储的数据进行比较的场效应晶体管和至少在数据信号与存储的数据进行比较时施加电流的符合检测信号线（25）。当数据信号与存储的数据一致时，晶体管（26）导通。晶体管（26）的数量等于输入的数据信号的数量。晶体管的漏极（260）并联连接，源极并联连接并以预定电压供电，通过集成电路，通过检测电位来检测输入的数据信号是否与存储的数据一致的一致检测信号线（25）。

7. 发明授权

US5907867A Translation lookaside buffer supporting multiple page sizes 失效
标题翻译：支持多页尺寸的翻译后备缓冲区
公开(公告)号：US5907867A
公开(公告)日：1999-05-25
申请号：US657231
申请日：1996-06-03
申请人： Toshinobu Shinbo , Suguru Tachibana , Susumu Narita , Shinichi Yoshioka , Koichiro Ishibashi , Hisayuki Higuchi , Yoshinobu Nakagome , Ikuya Kawasaki , Saneaki Tamaki
发明人： Toshinobu Shinbo , Suguru Tachibana , Susumu Narita , Shinichi Yoshioka , Koichiro Ishibashi , Hisayuki Higuchi , Yoshinobu Nakagome , Ikuya Kawasaki , Saneaki Tamaki
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , Y02B60/1225
摘要： A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.
摘要翻译：一种半导体集成电路装置，例如具有集相关翻译后备缓冲器（TLB）的数据处理装置。多个地址阵列各自具有用于存储表示页面大小的值的第二字段。从第二个字段读取的值用于通过比较器更改地址比较范围。多个数据阵列各自具有用于存储指定页面大小改变之后的页内地址或页码的位位置地址的第二字段。从地址阵列的第二个字段读取的值被用作第二选择器选择外部输入的虚拟地址的预定位置的地址或从数据阵列的每个第二场读取的地址的基础。所选地址作为物理地址输出。

8. 发明授权

US08508307B2 Oscillation circuit 有权
标题翻译：振荡电路
公开(公告)号：US08508307B2
公开(公告)日：2013-08-13
申请号：US13158054
申请日：2011-06-10
申请人： Kazuhiro Mitsuda , Koji Okada , Suguru Tachibana
发明人： Kazuhiro Mitsuda , Koji Okada , Suguru Tachibana
IPC分类号： H03L1/02 , H03K3/26 , H03K3/353
CPC分类号： H03L1/04 , G05F3/30 , H03K3/011 , H03K3/027
摘要： An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.
摘要翻译：一种包括参考电压产生电路的振荡电路，其将与绝对温度成比例增加的比例绝对温度（PTAT）输出添加到互补绝对温度（CTAT）输出，其降低与绝对温度成比例，以产生和输出参考电压。振荡电路产生具有期望和固定频率的振荡信号。

9. 发明授权

US08436687B2 Oscillating apparatus 有权
标题翻译：摆动装置
公开(公告)号：US08436687B2
公开(公告)日：2013-05-07
申请号：US12974996
申请日：2010-12-21
申请人： Kenta Aruga , Suguru Tachibana , Koji Okada
发明人： Kenta Aruga , Suguru Tachibana , Koji Okada
IPC分类号： H03K3/03
CPC分类号： H03K3/354
摘要： An oscillating apparatus includes: a transfer gate including a P-channel transistor and a N-channel transistor; a first inverter for inverting an output signal of the transfer gate and outputting the inverted output signal of the transfer gate; a second inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a third inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a fourth inverter for inverting the output signal of the third inverter and outputting the inverted output signal of the third inverter to an input-terminal of the transfer gate; a first capacitor connected between an output-terminal of the transfer gate and an output-terminal of the second inverter; and a second capacitor connected between the output-terminal of the transfer gate and a reference potential node.
摘要翻译：振荡装置包括：传输门，包括P沟道晶体管和N沟道晶体管; 第一反相器，用于反转传输门的输出信号并输出转移门的反相输出信号; 第二逆变器，用于反相第一反相器的输出信号，并输出第一反相器的反相输出信号; 第三反相器，用于反相第一反相器的输出信号并输出第一反相器的反相输出信号; 第四反相器，用于反相第三反相器的输出信号，并将第三反相器的反相输出信号输出到传输门的输入端; 连接在所述传输门的输出端和所述第二反相器的输出端之间的第一电容器; 以及连接在传输门的输出端和参考电位节点之间的第二电容器。

10. 发明申请

US20120075128A1 SUCCESSIVE APPROXIMATION A/D CONVERTER 有权
标题翻译：连续逼近A / D转换器
公开(公告)号：US20120075128A1
公开(公告)日：2012-03-29
申请号：US13186059
申请日：2011-07-19
申请人： Kenta ARUGA , Suguru Tachibana , Sanroku Tsukamoto , Koji Okada
发明人： Kenta ARUGA , Suguru Tachibana , Sanroku Tsukamoto , Koji Okada
IPC分类号： H03M1/12
CPC分类号： H03M1/1038 , H03M1/1019 , H03M1/144 , H03M1/468 , H03M1/765 , H03M1/804
摘要： A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.
摘要翻译：逐次逼近A / D转换器，具有耦合到顶部节点和开关组的电容元件组的主DAC; 比较上位节点电压和比较参考电压的比较器; 校正DAC根据要在主DAC中平衡的电容元件对的电容误差产生校正电压，并向顶部节点提供校正电压; 以及控制电路，产生用于控制开关组的内部数字输入和用于控制校正电压的校正码，并且当执行A / D转换时，通过比较器输出逐次逼近结果。控制电路测量要平衡的电容元件对的电容误差，并确定偏移消除的电容误差，其中在测量中产生的偏移从电容误差中消除。

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