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    • 4. 发明授权
    • Optical voltage sensor
    • 光电压传感器
    • US08829890B2
    • 2014-09-09
    • US12994701
    • 2009-05-27
    • Masao TakahashiJunichi SatoTakashi MiyabeTokihiro UmemuraTsuyoshi Kuwabara
    • Masao TakahashiJunichi SatoTakashi MiyabeTokihiro UmemuraTsuyoshi Kuwabara
    • G01R31/00
    • G01R15/242
    • A polarizing optical system (15, 16) is disposed perpendicular to an optical axis of incoming light from a light source (12), having the optical axis (12) as a center axis, and configured for polarization of incoming light to a prescribed reference state, an electro-optical device (17) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted, as a voltage to be measured is imposed thereon, to respond to the imposed voltage by polarizing light polarized by the polarizing optical system (15, 16), and an analyzer (18) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted for detection of light polarized by the electro-optical device (17), to irradiate a detector (21) configured for conversion of incoming light into an electric signal.
    • 偏振光学系统(15,16)垂直于来自光源(12)的入射光的光轴设置,所述光源(12)具有作为中心轴的光轴(12),并被配置为将入射光偏振到规定的参考 状态,电光装置(17)垂直于光轴设置,其光轴为中心轴,并且适于作为被测电压施加于其上以通过偏振光偏振来响应所施加的电压 通过所述偏振光学系统(15,16),并且分析器(18)垂直于所述光轴设置,所述分析器(18)具有所述光轴作为中心轴线,并适于检测由所述电光装置(17)偏振的光, 照射被配置为将入射光转换成电信号的检测器(21)。
    • 6. 发明申请
    • OPTICAL VOLTAGE SENSOR
    • 光电传感器
    • US20110234202A1
    • 2011-09-29
    • US12994701
    • 2009-05-27
    • Masao TakahashiJunichi SatoTakashi MiyabeTokihiro UmemuraTsuyoshi Kuwabara
    • Masao TakahashiJunichi SatoTakashi MiyabeTokihiro UmemuraTsuyoshi Kuwabara
    • G01R19/00
    • G01R15/242
    • A polarizing optical system (15, 16) is disposed perpendicular to an optical axis of incoming light from a light source (12), having the optical axis (12) as a center axis, and configured for polarization of incoming light to a prescribed reference state, an electro-optical device (17) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted, as a voltage to be measured is imposed thereon, to respond to the imposed voltage by polarizing light polarized by the polarizing optical system (15, 16), and an analyzer (18) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted for detection of light polarized by the electro-optical device (17), to irradiate a detector (21) configured for conversion of incoming light into an electric signal.
    • 偏振光学系统(15,16)垂直于来自光源(12)的入射光的光轴设置,所述光源(12)具有作为中心轴的光轴(12),并被配置为将入射光偏振到规定的参考 状态,电光装置(17)垂直于光轴设置,其光轴为中心轴,并且适于作为被测电压施加于其上以通过偏振光偏振来响应所施加的电压 通过所述偏振光学系统(15,16),并且分析器(18)垂直于所述光轴设置,所述分析器(18)具有所述光轴作为中心轴线,并适于检测由所述电光装置(17)偏振的光, 照射被配置为将入射光转换成电信号的检测器(21)。
    • 7. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20110079880A1
    • 2011-04-07
    • US12880764
    • 2010-09-13
    • Keiji MitaYasuhiro TamadaMasao TakahashiTakao Maruyama
    • Keiji MitaYasuhiro TamadaMasao TakahashiTakao Maruyama
    • H01L27/08
    • H01L29/8611H01L27/0814
    • A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1. An N+ type buried layer and an N+ type conductive layer are foamed to prevent an electric potential at the N+ type buried layer from becoming lower than an electric potential at a P+ type buried layer even when a large positive voltage is applied to the electrode AC1, so as to prevent a parasitic PNP transistor composed of the P+ type buried layer, the N+ type buried layer and the P type semiconductor substrate, that make an emitter, a base and a collector, respectively, from turning on.
    • 基于高耐压垂直PNP双极晶体管工艺技术,形成具有高耐受电压和低导通电阻的二极管串联二极管对。 两个二极管对并联连接形成桥,从而形成一个高效全波整流电路,该电路由于寄生晶体管而没有漏电流。 串联连接的二极管对通过连接由构成阳极的P型半导体衬底和形成阴极的N型掩埋层构成的二极管和由P +型导电层构成的二极管来形成, 阳极和N型外延层,其形成与电极AC1串联的阴极。 即使对电极AC1施加大的正电压,N +型掩埋层和N +型导电层发泡,以防止N +型掩埋层的电位变得低于P +型掩埋层的电位, 以防止分别形成发射极,基极和集电极的由P +型掩埋层,N +型掩埋层和P型半导体基板构成的寄生PNP晶体管导通。
    • 8. 发明申请
    • Bearing device
    • 轴承装置
    • US20100247011A1
    • 2010-09-30
    • US12592915
    • 2009-12-04
    • Yukitaka MuramotoMasaru KondoYasuaki GotoMasao Takahashi
    • Yukitaka MuramotoMasaru KondoYasuaki GotoMasao Takahashi
    • F16C17/04
    • F16C33/046F16C17/04F16C35/02F16C41/008F16C2360/22
    • In a bearing device 1, annular recesses 3a and 6a that house a thrust bearing 7 are formed in side surfaces of a housing 3 and a cap 6, a rotation preventing protrusion 12b is provided in an outer periphery of a lower side half-split thrust bearing 12 in the thrust bearing 7, and a rotation preventing groove 6b into which the rotation preventing protrusion 12b fits is formed in the annular recess 6a formed in the cap 6. The rotation preventing groove 6b is formed to be deeper than the annular recess 6a, and in a surface of the lower side half-split thrust bearing 12 on the side of the crank arm, a groove 12c is formed from the rotation preventing protrusion 12b to an inner peripheral portion of the lower side half-split thrust bearing 12. This can prevent partial contact of the thrust bearing, and prevent breakage due to stress concentration as much as possible.
    • 在轴承装置1中,容纳推力轴承7的环形凹部3a,6a形成在壳体3和盖6的侧面,防转动突起12b设置在下侧半分离推力 推力轴承7中的轴承12和形成在盖6中的环形凹部6a中形成有防止旋转突起12b嵌合的防旋转槽6b。防旋转槽6b形成为比环形凹部6a更深 ,并且在曲柄臂一侧的下侧半剖分推力轴承12的表面中,从防旋转突起12b向下侧半剖分推力轴承12的内周部形成有槽12c。 这可以防止推力轴承的部分接触,并且尽可能地防止由于应力集中而导致的断裂。
    • 9. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20090206376A1
    • 2009-08-20
    • US12333418
    • 2008-12-12
    • Keiji MitaMasao TakahashiTakao Arai
    • Keiji MitaMasao TakahashiTakao Arai
    • H01L29/78
    • H01L29/7322H01L29/735H01L29/8618
    • A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.
    • 常规的半导体器件具有以下问题:当在饱和区域中使用作为功率半导体元件的垂直PNP晶体管时,产生进入衬底的漏电流。 在本发明的半导体器件中,以N型扩散层为基底形成作为集电极区域的2个P型扩散层。 P型扩散层中的一个形成为具有比其他P型扩散层更低的杂质浓度和更窄的扩散宽度。 在这种结构中,当垂直PNP晶体管导通时,形成前者P型扩散层的区域主要用作寄生电流路径。 因此,防止由衬底,N型掩埋层和P型掩埋层构成的寄生晶体管导通,并且防止了进入衬底的漏电流。