专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06228720B1 Method for making insulated-gate semiconductor element 有权
标题翻译：制造绝缘栅半导体元件的方法
公开(公告)号：US06228720B1
公开(公告)日：2001-05-08
申请号：US09507714
申请日：2000-02-18
申请人： Makoto Kitabatake , Masao Uchida , Kunimasa Takahashi , Takeshi Uenoyama
发明人： Makoto Kitabatake , Masao Uchida , Kunimasa Takahashi , Takeshi Uenoyama
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/049 , H01L29/66068
摘要： An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film. With this method, the oxide film at the bottom surface of the concave portion is thicker than the oxide film at the side surfaces of the concave portion, so that a high breakdown voltage can be ensured, even when the surface of the silicon carbide layer is a face with which a superior epitaxial layer can be attained, such as the (111) Si-face of &bgr;-SiC or the (0001) Si-face of &agr;-SiC.
摘要翻译：提供了具有沟槽结构的绝缘栅半导体元件，即使使用优选获得具有良好特性的半导体元件的碳化硅衬底，其具有高的击穿电压。蚀刻碳化硅衬底的表面以形成凹部。然后，从上方照射粒子束，例如离子束，至少在凹部的底面形成有缺陷层。在氧化气氛中加热基板，至少在凹部的侧面和底面形成氧化膜。然后，在氧化膜上形成栅电极。通过该方法，凹部底面的氧化膜比凹部的侧面的氧化膜厚，因此即使当碳化硅层的表面为可以获得优异的外延层的面，例如β-SiC的（111）Si面或α-SiC的（0001）Si面。

2. 发明授权

US06989553B2 Semiconductor device having an active region of alternating layers 有权
标题翻译：具有交替层的有源区的半导体器件
公开(公告)号：US06989553B2
公开(公告)日：2006-01-24
申请号：US10625256
申请日：2003-07-23
申请人： Toshiya Yokogawa , Kunimasa Takahashi , Osamu Kusumoto , Makoto Kitabatake , Takeshi Uenoyama
发明人： Toshiya Yokogawa , Kunimasa Takahashi , Osamu Kusumoto , Makoto Kitabatake , Takeshi Uenoyama
IPC分类号： H01L31/0312
CPC分类号： H01L29/155 , H01L29/045 , H01L29/1608 , H01L29/2003 , H01L29/365 , H01L29/812 , H01L29/872
摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.
摘要翻译：有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

3. 发明授权

US06864507B2 MISFET 有权
公开(公告)号：US06864507B2
公开(公告)日：2005-03-08
申请号：US10459807
申请日：2003-06-12
申请人： Toshiya Yokogawa , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Takeshi Uenoyama
发明人： Toshiya Yokogawa , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Takeshi Uenoyama
IPC分类号： H01L21/04 , H01L29/10 , H01L29/24 , H01L29/36 , H01L29/772 , H01L29/78 , H01L31/0312
CPC分类号： H01L29/7813 , H01L21/0455 , H01L29/105 , H01L29/1608 , H01L29/365 , H01L29/66068 , H01L29/7725 , H01L29/78 , H01L29/7828 , H01L29/7838
摘要： P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.
摘要翻译： P型有源区12; n型源极/漏极区域13a和13b; 由热氧化膜制成的栅极绝缘膜14; 栅电极15; 源极/漏电极16a和16b设置在p型SiC衬底11上。在有源区12中，足够薄以产生量子效应的p型重掺杂层12a和厚的未掺杂层12b交替堆叠当载流子流动时，杂质离子在有源区中的散射减小，并且沟道迁移率增加。在OFF状态下，耗尽层在整个有源区扩展，并且击穿电压增加。由于栅极绝缘膜中俘获的电荷减少或栅极绝缘膜与有源区之间的界面附近的结果，沟道迁移率进一步增加。

4. 发明授权

US06690035B1 Semiconductor device having an active region of alternating layers 有权
标题翻译：具有交替层的有源区的半导体器件
公开(公告)号：US06690035B1
公开(公告)日：2004-02-10
申请号：US09980598
申请日：2001-11-01
申请人： Toshiya Yokogawa , Kunimasa Takahashi , Osamu Kusumoto , Makoto Kitabatake , Takeshi Uenoyama
发明人： Toshiya Yokogawa , Kunimasa Takahashi , Osamu Kusumoto , Makoto Kitabatake , Takeshi Uenoyama
IPC分类号： H01L310312
CPC分类号： H01L29/155 , H01L29/045 , H01L29/1608 , H01L29/2003 , H01L29/365 , H01L29/812 , H01L29/872
摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.
摘要翻译：有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

5. 发明授权

US06674131B2 Semiconductor power device for high-temperature applications 失效
标题翻译：半导体功率器件用于高温应用
公开(公告)号：US06674131B2
公开(公告)日：2004-01-06
申请号：US10069654
申请日：2002-02-26
申请人： Toshiya Yokogawa , Kunimasa Takahashi , Makoto Kitabatake , Osamu Kusumoto , Takeshi Uenoyama , Koji Miyazaki
发明人： Toshiya Yokogawa , Kunimasa Takahashi , Makoto Kitabatake , Osamu Kusumoto , Takeshi Uenoyama , Koji Miyazaki
IPC分类号： H01L29423
CPC分类号： H01L21/8213 , H01L21/8252 , H01L27/0629 , H01L27/0688 , H01L29/105 , H01L29/157 , H01L29/1608 , H01L29/365 , H01L29/7725 , H01L29/7838 , H01L29/812 , H01L29/872 , Y10S438/931 , Y10S438/957
摘要： In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.
摘要翻译：在SiC衬底（10）中，交替堆叠由n型重掺杂层（12a）和未掺杂层（12b）组成的第一有源区（12）和由p-型衬底构成的第二有源区（13）交替层叠的重掺杂层（13a）和未掺杂层（13b）按顺序向上设置。肖特基二极管（20）和pMOSFET（30）设置在第一有源区（12）上。在第二有源区域（13）上设置有nMOSFET（40），电容器（50）和电感器（60）。肖特基二极管（20）和MOSFET（30,40）由于由δ掺杂层和未掺杂层组成的多层结构而具有击穿电压特性和载流子特性，并且集成在公共衬底中。

6. 发明授权

US06617653B1 MISFET 有权
公开(公告)号：US06617653B1
公开(公告)日：2003-09-09
申请号：US10048344
申请日：2002-01-30
申请人： Toshiya Yokogawa , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Takeshi Uenoyama
发明人： Toshiya Yokogawa , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Takeshi Uenoyama
IPC分类号： H01L2994
CPC分类号： H01L29/7813 , H01L21/0455 , H01L29/105 , H01L29/1608 , H01L29/365 , H01L29/66068 , H01L29/7725 , H01L29/78 , H01L29/7828 , H01L29/7838
摘要： P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.

7. 发明授权

US07816688B2 Semiconductor device and production method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07816688B2
公开(公告)日：2010-10-19
申请号：US10494616
申请日：2002-11-27
申请人： Kenya Yamashita , Makoto Kitabatake , Kunimasa Takahashi , Osamu Kusumoto , Masao Uchida , Ryoko Miyanaga
发明人： Kenya Yamashita , Makoto Kitabatake , Kunimasa Takahashi , Osamu Kusumoto , Masao Uchida , Ryoko Miyanaga
IPC分类号： H01L29/51
CPC分类号： H01L21/28185 , H01L21/049 , H01L21/28202 , H01L29/1608 , H01L29/41766 , H01L29/513 , H01L29/518 , H01L29/66068 , H01L29/78 , H01L29/7802 , H01L29/7838
摘要： An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.
摘要翻译： SIC基板1的上部在氧气气氛中在800〜1400℃的温度下氧化，在1.4×102Pa以下，由此形成作为热氧化膜的第一绝缘膜2 nm以下的厚度。然后，进行退火，然后通过CVD在其上形成厚度为约5nm的氮化物膜的第一盖层3。作为厚度约130nm的氧化物膜的第二绝缘膜4通过CVD沉积在其上。在其上形成厚度为约10nm的氮化膜的第二盖层5。以这种方式，形成通过第二盖层5由第一绝缘膜2制成的栅极绝缘膜6，从而获得低损耗高可靠性的半导体器件。

8. 发明授权

US07786565B2 Semiconductor apparatus including power semiconductor device constructed by using wide band gap semiconductor 有权
标题翻译：包括通过使用宽带隙半导体构成的功率半导体器件的半导体装置
公开(公告)号：US07786565B2
公开(公告)日：2010-08-31
申请号：US10536828
申请日：2004-09-06
申请人： Makoto Kitabatake , Osamu Kusumoto , Masao Uchida , Kunimasa Takahashi , Kenya Yamashita
发明人： Makoto Kitabatake , Osamu Kusumoto , Masao Uchida , Kunimasa Takahashi , Kenya Yamashita
IPC分类号： H01L23/492
CPC分类号： H01L23/3735 , H01L23/3672 , H01L23/4334 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01004 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/1301 , H01L2924/13055 , H01L2924/13062 , H01L2924/13063 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.
摘要翻译：半导体装置包括半导体芯片61，其包括使用宽带隙半导体的功率半导体器件，基底材料62和63，第一和第二中间构件65和68a，导热构件66，辐射翅片67和封装材料用于封装半导体芯片61，第一和第二中间构件65和68a以及导热构件66.基材62和63的顶端分别作为外部连接端子62a和63a工作。第二中间构件68a由比第一中间构件65低导热性的材料制成，并且与第一中间构件相比，第二中间构件68a的与半导体芯片61的接触面积更大。

9. 发明授权

US06995397B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06995397B2
公开(公告)日：2006-02-07
申请号：US10466353
申请日：2002-09-17
申请人： Kenya Yamashita , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Masao Uchida , Ryoko Miyanaga
发明人： Kenya Yamashita , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Masao Uchida , Ryoko Miyanaga
IPC分类号： H01L31/072
CPC分类号： H01L29/66068 , H01L29/105 , H01L29/1608 , H01L29/365 , H01L29/7725 , H01L29/7828 , H01L29/7838
摘要： A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a δ doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration δ doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.
摘要翻译：具有堆积通道SiC-MISFET结构的半导体器件包括形成在SiC衬底上的p型SiC层10，n型沟道层20，栅极绝缘膜11，栅电极12和n型源，漏极层13a和13b。沟道层20包括未掺杂层22和形成在未掺杂层22的下端附近的δ掺杂层21.由于沟道层20在其较深部分包括高浓度δ掺杂层21，沟道层的表面区域的电场减弱，从而允许电流驱动力增加。

10. 发明授权

US06270573B1 Silicon carbide substrate, and method for producing the substrate, and semiconductor device utilizing the substrate 失效
标题翻译：碳化硅基板及其制造方法以及使用该基板的半导体装置
公开(公告)号：US06270573B1
公开(公告)日：2001-08-07
申请号：US09297129
申请日：1999-04-26
申请人： Makoto Kitabatake , Masao Uchida , Kunimasa Takahashi
发明人： Makoto Kitabatake , Masao Uchida , Kunimasa Takahashi
IPC分类号： C30B2518
CPC分类号： H01L29/1608 , C30B23/02 , C30B29/36 , H01L29/045 , H01L29/1075 , H01L29/66068 , Y10S117/913 , Y10T428/12576 , Y10T428/12674
摘要： A silicon carbide thin film is epitaxially grown by an MBE or the like method with silicon atoms 2 being maintained to be in excess of carbon atoms on a growth surface 1a of a silicon carbide crystal in a substrate 1. A silicon carbide substrate with a good crystallinity is thereby achieved at a low temperature with a good reproducibility. This crystal growth is possible at a low temperature of 1300° C. or lower, and the productions of a high-concentration doped film, a selectively grown film, and a grown film of a cubic silicon carbide on a hexagonal crystal are achieved. In crystallizing a cubic silicon carbide on a hexagonal crystal, the use of an off-cut surface inclined towards a direction is effective to prevent an occurrence of twin.
摘要翻译：通过在基板1中的碳化硅晶体的生长面1a上保持硅原子2保持为超过碳原子的MBE等外观生长碳化硅薄膜。具有良好的碳化硅基板从而在低温下实现了结晶度的良好的再现性。可以在1300℃以下的低温下进行晶体生长，可以实现六方晶的高浓度掺杂膜，选择性生长膜和立方碳化硅生长膜的制备。在六方晶上结晶立方碳化硅时，使用朝向<1 {overscore（1）} 00>方向倾斜的偏斜表面是有效的，以防止双胞胎发生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式