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1. 发明授权

US5025229A Voltage-controlled oscillator using a surface elastic wave resonator 失效
标题翻译：使用表面弹性波谐振器的压控振荡器
公开(公告)号：US5025229A
公开(公告)日：1991-06-18
申请号：US528079
申请日：1990-05-24
申请人： Makoto Hasegawa , Kazuaki Takahashi , Mitsuo Makimoto , Masao Takahashi , Takayuki Shimazu
发明人： Makoto Hasegawa , Kazuaki Takahashi , Mitsuo Makimoto , Masao Takahashi , Takayuki Shimazu
IPC分类号： H03B5/30 , H03B5/32 , H03B5/36
CPC分类号： H03B5/368 , H03B5/32 , H03B5/326 , H03B2200/0008 , H03B2200/0026 , H03B2200/004
摘要： A Colpitts oscillator has an integrated circuit. The integrated circuit includes a transistor having an equivalent large size, a bypass capacitor connected between a collector of the transistor and a ground, a first feedback capacitor connected between a base and an emitter of the transistor, a second feedback capacitor connected between the emitter of the transistor and the ground, and an emitter follower connected to the emitter of the transistor. In a package, a stray reactance and a bonding wire are designed so as to agree with an element value and a Q value which can be used as parts of a resonator. A surface elastic wave resonator disposed outside the integrated circuit is connected between the base of the transistor and the ground. The oscillator is voltage controlled by a variable capacitance diode connected in series with the resonator.
摘要翻译： Colpitts振荡器具有集成电路。集成电路包括具有等效大尺寸的晶体管，连接在晶体管的集电极和地之间的旁路电容器，连接在晶体管的基极和发射极之间的第一反馈电容器，连接在晶体管的基极和发射极之间的第二反馈电容器，晶体管和地，以及连接到晶体管的发射极的射极跟随器。在封装中，杂散电抗和接合线被设计成与可以用作谐振器的一部分的元件值和Q值一致。设置在集成电路外部的表面弹性波谐振器连接在晶体管的基极与地之间。振荡器由与谐振器串联连接的可变电容二极管进行电压控制。

2. 发明授权

US10377902B2 Crystallized red pigment, method of producing a recrystallized red pigment and a method for improving the appearance of or preventing wrinkles 有权
公开(公告)号：US10377902B2
公开(公告)日：2019-08-13
申请号：US14786748
申请日：2013-10-04
申请人： HEIMAT CO., LTD. , Masao Takahashi , TOKIWA PHYTOCHEMICAL CO., LTD.
发明人： Masao Takahashi , Nobuhito Kimura
IPC分类号： A61K36/00 , C09B61/00 , A61Q19/08 , A61K8/97 , A61K31/352 , A61K36/889 , C09B57/02 , C09B67/46 , A23L5/42 , A23L33/105 , A61K8/49 , A61K31/353
摘要： A crystalized red pigment of saw palmetto fruit obtained by extracting a saw palmetto fruit with ethanol and depositing a red pigment in the extract.

3. 发明授权

US08829890B2 Optical voltage sensor 有权
标题翻译：光电压传感器
公开(公告)号：US08829890B2
公开(公告)日：2014-09-09
申请号：US12994701
申请日：2009-05-27
申请人： Masao Takahashi , Junichi Sato , Takashi Miyabe , Tokihiro Umemura , Tsuyoshi Kuwabara
发明人： Masao Takahashi , Junichi Sato , Takashi Miyabe , Tokihiro Umemura , Tsuyoshi Kuwabara
IPC分类号： G01R31/00
CPC分类号： G01R15/242
摘要： A polarizing optical system (15, 16) is disposed perpendicular to an optical axis of incoming light from a light source (12), having the optical axis (12) as a center axis, and configured for polarization of incoming light to a prescribed reference state, an electro-optical device (17) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted, as a voltage to be measured is imposed thereon, to respond to the imposed voltage by polarizing light polarized by the polarizing optical system (15, 16), and an analyzer (18) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted for detection of light polarized by the electro-optical device (17), to irradiate a detector (21) configured for conversion of incoming light into an electric signal.
摘要翻译：偏振光学系统（15,16）垂直于来自光源（12）的入射光的光轴设置，所述光源（12）具有作为中心轴的光轴（12），并被配置为将入射光偏振到规定的参考状态，电光装置（17）垂直于光轴设置，其光轴为中心轴，并且适于作为被测电压施加于其上以通过偏振光偏振来响应所施加的电压通过所述偏振光学系统（15,16），并且分析器（18）垂直于所述光轴设置，所述分析器（18）具有所述光轴作为中心轴线，并适于检测由所述电光装置（17）偏振的光，照射被配置为将入射光转换成电信号的检测器（21）。

4. 发明申请

US20120080780A1 SEM ICONDUCTOR DEVICE HAVING PADS AND WHICH MINIMIZES DEFECTS DUE TO BONDING AND PROBING PROCESSES 有权
标题翻译：具有垫片的SEM电极器件和由于结合和探测过程而导致的缺陷最小化
公开(公告)号：US20120080780A1
公开(公告)日：2012-04-05
申请号：US13323454
申请日：2011-12-12
申请人： Koji TAKEMURA , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
发明人： Koji TAKEMURA , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01079 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
摘要翻译：半导体器件包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在第一层间绝缘膜上方的焊盘; 以及在位于所述垫下方的所述第一层间绝缘膜的部分中彼此间隔开的多个第一互连。在焊盘下面，第一互连以四边形的平面形状形成。

5. 发明申请

US20110234202A1 OPTICAL VOLTAGE SENSOR 有权
标题翻译：光电传感器
公开(公告)号：US20110234202A1
公开(公告)日：2011-09-29
申请号：US12994701
申请日：2009-05-27
申请人： Masao Takahashi , Junichi Sato , Takashi Miyabe , Tokihiro Umemura , Tsuyoshi Kuwabara
发明人： Masao Takahashi , Junichi Sato , Takashi Miyabe , Tokihiro Umemura , Tsuyoshi Kuwabara
IPC分类号： G01R19/00
CPC分类号： G01R15/242
摘要： A polarizing optical system (15, 16) is disposed perpendicular to an optical axis of incoming light from a light source (12), having the optical axis (12) as a center axis, and configured for polarization of incoming light to a prescribed reference state, an electro-optical device (17) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted, as a voltage to be measured is imposed thereon, to respond to the imposed voltage by polarizing light polarized by the polarizing optical system (15, 16), and an analyzer (18) is disposed perpendicular to the optical axis, having the optical axis as a center axis, and adapted for detection of light polarized by the electro-optical device (17), to irradiate a detector (21) configured for conversion of incoming light into an electric signal.
摘要翻译：偏振光学系统（15,16）垂直于来自光源（12）的入射光的光轴设置，所述光源（12）具有作为中心轴的光轴（12），并被配置为将入射光偏振到规定的参考状态，电光装置（17）垂直于光轴设置，其光轴为中心轴，并且适于作为被测电压施加于其上以通过偏振光偏振来响应所施加的电压通过所述偏振光学系统（15,16），并且分析器（18）垂直于所述光轴设置，所述分析器（18）具有所述光轴作为中心轴线，并适于检测由所述电光装置（17）偏振的光，照射被配置为将入射光转换成电信号的检测器（21）。

6. 发明申请

US20110079880A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110079880A1
公开(公告)日：2011-04-07
申请号：US12880764
申请日：2010-09-13
申请人： Keiji Mita , Yasuhiro Tamada , Masao Takahashi , Takao Maruyama
发明人： Keiji Mita , Yasuhiro Tamada , Masao Takahashi , Takao Maruyama
IPC分类号： H01L27/08
CPC分类号： H01L29/8611 , H01L27/0814
摘要： A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1. An N+ type buried layer and an N+ type conductive layer are foamed to prevent an electric potential at the N+ type buried layer from becoming lower than an electric potential at a P+ type buried layer even when a large positive voltage is applied to the electrode AC1, so as to prevent a parasitic PNP transistor composed of the P+ type buried layer, the N+ type buried layer and the P type semiconductor substrate, that make an emitter, a base and a collector, respectively, from turning on.
摘要翻译：基于高耐压垂直PNP双极晶体管工艺技术，形成具有高耐受电压和低导通电阻的二极管串联二极管对。两个二极管对并联连接形成桥，从而形成一个高效全波整流电路，该电路由于寄生晶体管而没有漏电流。串联连接的二极管对通过连接由构成阳极的P型半导体衬底和形成阴极的N型掩埋层构成的二极管和由P +型导电层构成的二极管来形成，阳极和N型外延层，其形成与电极AC1串联的阴极。即使对电极AC1施加大的正电压，N +型掩埋层和N +型导电层发泡，以防止N +型掩埋层的电位变得低于P +型掩埋层的电位，以防止分别形成发射极，基极和集电极的由P +型掩埋层，N +型掩埋层和P型半导体基板构成的寄生PNP晶体管导通。

7. 发明申请

US20100247011A1 Bearing device 有权
标题翻译：轴承装置
公开(公告)号：US20100247011A1
公开(公告)日：2010-09-30
申请号：US12592915
申请日：2009-12-04
申请人： Yukitaka Muramoto , Masaru Kondo , Yasuaki Goto , Masao Takahashi
发明人： Yukitaka Muramoto , Masaru Kondo , Yasuaki Goto , Masao Takahashi
IPC分类号： F16C17/04
CPC分类号： F16C33/046 , F16C17/04 , F16C35/02 , F16C41/008 , F16C2360/22
摘要： In a bearing device 1, annular recesses 3a and 6a that house a thrust bearing 7 are formed in side surfaces of a housing 3 and a cap 6, a rotation preventing protrusion 12b is provided in an outer periphery of a lower side half-split thrust bearing 12 in the thrust bearing 7, and a rotation preventing groove 6b into which the rotation preventing protrusion 12b fits is formed in the annular recess 6a formed in the cap 6. The rotation preventing groove 6b is formed to be deeper than the annular recess 6a, and in a surface of the lower side half-split thrust bearing 12 on the side of the crank arm, a groove 12c is formed from the rotation preventing protrusion 12b to an inner peripheral portion of the lower side half-split thrust bearing 12. This can prevent partial contact of the thrust bearing, and prevent breakage due to stress concentration as much as possible.
摘要翻译：在轴承装置1中，容纳推力轴承7的环形凹部3a，6a形成在壳体3和盖6的侧面，防转动突起12b设置在下侧半分离推力推力轴承7中的轴承12和形成在盖6中的环形凹部6a中形成有防止旋转突起12b嵌合的防旋转槽6b。防旋转槽6b形成为比环形凹部6a更深，并且在曲柄臂一侧的下侧半剖分推力轴承12的表面中，从防旋转突起12b向下侧半剖分推力轴承12的内周部形成有槽12c。这可以防止推力轴承的部分接触，并且尽可能地防止由于应力集中而导致的断裂。

8. 发明申请

US20090206376A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090206376A1
公开(公告)日：2009-08-20
申请号：US12333418
申请日：2008-12-12
申请人： Keiji Mita , Masao Takahashi , Takao Arai
发明人： Keiji Mita , Masao Takahashi , Takao Arai
IPC分类号： H01L29/78
CPC分类号： H01L29/7322 , H01L29/735 , H01L29/8618
摘要： A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.
摘要翻译：常规的半导体器件具有以下问题：当在饱和区域中使用作为功率半导体元件的垂直PNP晶体管时，产生进入衬底的漏电流。在本发明的半导体器件中，以N型扩散层为基底形成作为集电极区域的2个P型扩散层。 P型扩散层中的一个形成为具有比其他P型扩散层更低的杂质浓度和更窄的扩散宽度。在这种结构中，当垂直PNP晶体管导通时，形成前者P型扩散层的区域主要用作寄生电流路径。因此，防止由衬底，N型掩埋层和P型掩埋层构成的寄生晶体管导通，并且防止了进入衬底的漏电流。

9. 发明授权

US07538433B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07538433B2
公开(公告)日：2009-05-26
申请号：US11452957
申请日：2006-06-15
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
IPC分类号： H01L23/52
CPC分类号： H01L23/585 , H01L21/76832 , H01L23/522 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
摘要翻译：一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强靠近密封圈。芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层使用通孔部分。

10. 发明申请

US20070001308A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070001308A1
公开(公告)日：2007-01-04
申请号：US11452957
申请日：2006-06-15
申请人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
发明人： Koji Takemura , Hiroshige Hirano , Yutaka Itoh , Hikari Sano , Masao Takahashi , Koji Koike
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/585 , H01L21/76832 , H01L23/522 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
摘要翻译：一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强靠近密封圈。芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层使用通孔部分。

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