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1. 发明授权

US5740401A Multiprocessor system having a processor invalidating operand cache when lock-accessing 失效
标题翻译：具有处理器的多处理器系统在锁定访问时使操作数缓存无效
公开(公告)号：US5740401A
公开(公告)日：1998-04-14
申请号：US9077
申请日：1993-01-26
申请人： Makoto Hanawa , Tadahiko Nishimukai , Osamu Nishii , Makoto Suzuki
发明人： Makoto Hanawa , Tadahiko Nishimukai , Osamu Nishii , Makoto Suzuki
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F12/08 , G06F12/14 , G06F15/177
CPC分类号： G06F9/52 , G06F12/0806 , G06F12/1466
摘要： A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.
摘要翻译：多处理器系统包括地址总线170，数据总线180，处理器110和120，访问队列135和145，共享存储器130和140以及锁定控制电路500和510.特别地，锁定指示标志寄存器501是当一个处理器110中的操作数高速缓存112正在对共享存储器130的预定地址进行锁定访问时，标志寄存器501是基于锁定命令信号260设置的，在另一个处理器120中的指令高速缓存122到共享存储器130的预定地址的访问是被禁止的，但是在锁定访问时允许访问不同的地址。在锁定访问被释放之后，锁定控制电路500接受对预定地址的访问。

2. 发明授权

US6078983A Multiprocessor system having distinct data bus and address bus arbiters 失效
标题翻译：具有不同数据总线和地址总线仲裁器的多处理器系统
公开(公告)号：US6078983A
公开(公告)日：2000-06-20
申请号：US862322
申请日：1997-05-23
申请人： Makoto Hanawa , Tadahiko Nishimukai , Osamu Nishii , Makoto Suzuki
发明人： Makoto Hanawa , Tadahiko Nishimukai , Osamu Nishii , Makoto Suzuki
IPC分类号： G06F15/16 , G06F12/00 , G06F12/06 , G06F13/16 , G06F15/167 , G06F15/177 , G06F13/36
CPC分类号： G06F13/1642 , G06F13/1605
摘要： A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.
摘要翻译：本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列，第一和第二仲裁器以及被划分成四个存储体的共享存储器。四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。当处理器需要来自存储体的数据时，处理器发送具有数据访问请求的处理器ID。当存储体返回数据时，存储体输出请求发起者的处理器ID和所需的数据。即使连续访问请求被寻址到共享存储器的一个组，请求的后续访问也不需要等待先前的访问请求完成。据说，系统的吞吐量可以大大提高。第一和第二仲裁者用于决定公共汽车的所有权。

3. 发明授权

US5375215A Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank 失效
标题翻译：具有被分成多个存储体的共享存储器的多处理器系统具有对应于每个存储体的访问队列
公开(公告)号：US5375215A
公开(公告)日：1994-12-20
申请号：US784546
申请日：1991-10-29
申请人： Makoto Hanawa , Tadahiko Nishimukai , Osamu Nishii , Makoto Suzuki
发明人： Makoto Hanawa , Tadahiko Nishimukai , Osamu Nishii , Makoto Suzuki
IPC分类号： G06F15/16 , G06F12/00 , G06F12/06 , G06F13/16 , G06F15/167 , G06F15/177 , G06F13/36 , G06F9/40
CPC分类号： G06F13/1642 , G06F13/1605
摘要： A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.
摘要翻译：本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列和被划分为四个存储体的共享存储器。四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。即使连续访问请求被寻址到共享存储器的一个存储体，后续访问请求也不需要等待先前访问请求完成。因此，可以大大提高系统的吞吐量。

4. 发明授权

US5253197A Semiconductor associative memory device with current sensing 失效
标题翻译：具有电流检测的半导体联想存储器件
公开(公告)号：US5253197A
公开(公告)日：1993-10-12
申请号：US580464
申请日：1990-09-11
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04
CPC分类号： G11C15/04 , G06F12/0895 , G06F12/1054 , Y02B60/1225
摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
摘要翻译：在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成电压信息。在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测能力也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

5. 发明授权

US5381531A Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction 失效
标题翻译：用于选择性地同时执行延迟槽指令的数据处理器和在条件分支指令之后的第二后续指令
公开(公告)号：US5381531A
公开(公告)日：1995-01-10
申请号：US727581
申请日：1991-07-09
申请人： Makoto Hanawa , Tadahiko Nishimukai , Makoto Suzuki , Katsuhiro Shimohigashi
发明人： Makoto Hanawa , Tadahiko Nishimukai , Makoto Suzuki , Katsuhiro Shimohigashi
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3885
摘要： An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.
摘要翻译：能够同时执行两个指令的数据处理器（610）的指令获取单元（640）在一个周期中从存储器（620）获取第一和第二指令。在第一和第二指令解码器（644,645）中被解码之前，这样取得的第一和第二指令被设置在第一和第二寄存器（641,642）中。比较器（131,132）将第一指令的目的地字段的数据与第二指令的源字段上的数据进行比较。当两个数据不一致时，并行操作控制单元（646）允许第一和第二指令下的第一和第二指令执行单元（651,652）响应于比较器的输出执行两个指令（ 131,132）。当两个数据一致时，并行操作控制单元（646）禁止并行执行。

6. 发明授权

US09176462B2 Image forming apparatus having a drawer unit with a paper-feeding conveying path therein 有权
标题翻译：图像形成装置具有其中具有送纸输送路径的抽屉单元
公开(公告)号：US09176462B2
公开(公告)日：2015-11-03
申请号：US14102747
申请日：2013-12-11
申请人： Yoshihide Ohta , Joh Ebara , Hiroshi Ishii , Junichi Kawase , Kohta Takenaka , Tetsuji Nishikawa , Kohta Hirakawa , Toshihiro Shimada , Yusuke Funayama , Tsuyoshi Endo , Yusuke Masu , Makoto Suzuki
发明人： Yoshihide Ohta , Joh Ebara , Hiroshi Ishii , Junichi Kawase , Kohta Takenaka , Tetsuji Nishikawa , Kohta Hirakawa , Toshihiro Shimada , Yusuke Funayama , Tsuyoshi Endo , Yusuke Masu , Makoto Suzuki
IPC分类号： G03G15/00 , G03G21/00 , G03G21/16
CPC分类号： G03G21/1623 , G03G15/6502 , G03G21/1638 , G03G21/1647 , G03G21/1695 , G03G2215/00544 , G03G2215/00713 , G03G2221/1675
摘要： An image forming apparatus having a drawer unit that includes therein a paper-feeding conveying path for conveying a recording medium conveyed from a paper feeding unit on which the recording media are stacked to an image forming unit and/or a discharge conveying path for conveying the recording medium on which an image has been formed to a discharging unit, and be drawn out from an apparatus main body; a lock unit that locks the drawer unit to the apparatus main body; a straddle detecting unit that detects whether the recording medium straddles a conveying path in the apparatus main body and a conveying path in the drawer unit; and a controller that controls the lock unit to lock the drawer unit to the apparatus main body when the straddle detecting unit detects the straddle.
摘要翻译：一种具有抽屉单元的图像形成装置，其中包括一个送纸传送路径，用于将从其上叠放有记录介质的供纸单元输送的记录介质传送到图像形成单元和/或排出传送路径，用于传送已经形成图像的记录介质到排出单元，并从设备主体被拉出; 锁定单元，其将抽屉单元锁定到设备主体; 跨越检测单元，其检测记录介质是否跨越所述设备主体中的传送路径和所述抽屉单元中的传送路径; 以及控制器，当所述跨骑式检测单元检测到所述跨骑时，所述控制器控制所述锁定单元将所述抽屉单元锁定到所述装置主体。

7. 发明授权

US08047165B2 Medium circulating apparatus for improving startability and warm up ability 失效
标题翻译：中等循环设备，提高启动性和预热能力
公开(公告)号：US08047165B2
公开(公告)日：2011-11-01
申请号：US11922141
申请日：2006-06-05
申请人： Yasushi Ito , Makoto Suzuki , Kenichi Yamada , Rentaro Kuroki , Tomohiro Shinagawa
发明人： Yasushi Ito , Makoto Suzuki , Kenichi Yamada , Rentaro Kuroki , Tomohiro Shinagawa
IPC分类号： F01P9/00
CPC分类号： F01M5/02 , F01P9/00 , F16H57/0412 , F16N39/00
摘要： A medium circulating apparatus of engine oil, which improves startability and warm up ability of an internal combustion engine, includes a microbubble generator that generates microbubbles and mixes the microbubbles into the circulating engine oil. Further, the medium circulating apparatus includes a medium temperature acquiring unit that acquires a temperature of the engine oil. The microbubbles are generated by the microbubble generator when the temperature of the engine oil is less than or equal to a predetermined value in order to decrease a viscosity, a heat conductivity, and a heat capacity of the engine oil in which the microbubbles are mixed.
摘要翻译：发动机油的介质循环装置，其提高内燃机的起动性和预热能力，包括产生微泡并将微泡混入循环发动机油的微泡发生器。此外，介质循环装置包括获取发动机油的温度的介质温度获取单元。为了降低混合微泡的发动机油的粘度，导热性和热容量，当发动机机油的温度小于或等于预定值时，微泡由微泡发生器产生。

8. 发明授权

US08024757B2 Digital broadcast receiver and backup method 失效
标题翻译：数字广播接收机和备份方式
公开(公告)号：US08024757B2
公开(公告)日：2011-09-20
申请号：US10432659
申请日：2002-09-20
申请人： Kaoru Nara , Makoto Suzuki
发明人： Kaoru Nara , Makoto Suzuki
IPC分类号： G06F3/00 , G06F13/00 , H04N5/445
CPC分类号： H04H60/47 , G11B27/032 , G11B27/034 , G11B27/105 , G11B27/34 , G11B27/36 , G11B2220/20 , G11B2220/455 , G11B2220/90 , H04H60/27 , H04N5/76 , H04N5/765 , H04N5/775 , H04N5/781
摘要： A digital broadcast receiver capable of reducing time and labor to back-up contents recorded on one recording medium to another recording medium. A digital broadcast receiver extracts the contents recorded, out of order, on a first recording medium by an extracting unit according to the titles or genres recorded in a content list, and automatically rearranges the extracted contents using an arranging unit according to video-recording date-and-hour recorded in the content list, for recording as a content list onto a second recording medium (300).
摘要翻译：一种数字广播接收机，其能够减少记录在一个记录介质上的内容备份到另一个记录介质的时间和人力。数字广播接收机根据记录在内容列表中的标题或类型，通过提取单元在第一记录介质上提取记录在第一记录介质上的内容，并且使用根据视频记录日期的排列单元自动重新排列所提取的内容记录在内容列表中的小时，用于作为内容列表记录到第二记录介质（300）上。

9. 发明授权

US07960305B2 Polymerization catalyst composition and process for production of polymer 有权
标题翻译：聚合催化剂组合物和聚合物生产方法
公开(公告)号：US07960305B2
公开(公告)日：2011-06-14
申请号：US11884941
申请日：2006-02-21
申请人： Makoto Suzuki , Yoshihisa Inoue , Tadahito Nobori , Yoshihiro Yamamoto
发明人： Makoto Suzuki , Yoshihisa Inoue , Tadahito Nobori , Yoshihiro Yamamoto
IPC分类号： C08F4/44 , B01J31/18
CPC分类号： C08F10/00 , C08F4/00 , C08F4/26 , C08F4/40 , C08F112/08 , C08F120/14 , C08F120/18
摘要： A polymerization catalyst composition for a radically polymerizable monomer of the present invention comprises a transition metal-containing phosphazenium composition which is produced by mixing a phosphazenium compound with a compound of a transition metal belonging to Groups 4 to 12 in the periodic table and an organic halogen compound.
摘要翻译：本发明的自由基聚合性单体的聚合催化剂组合物含有通过将磷氮烯基鏻化合物与属于周期表中第4〜12族的过渡金属的化合物和有机卤素复合。

10. 发明授权

US07923083B2 Recording medium, ink composition and recording method using the same 失效
标题翻译：记录介质，油墨组成和使用其的记录方法
公开(公告)号：US07923083B2
公开(公告)日：2011-04-12
申请号：US11157078
申请日：2005-06-21
申请人： Kaoru Tojo , Toshiki Taguchi , Yoshiharu Yabuki , Makoto Suzuki
发明人： Kaoru Tojo , Toshiki Taguchi , Yoshiharu Yabuki , Makoto Suzuki
IPC分类号： B41M5/40
CPC分类号： C09D11/40 , B41M5/5227 , B41M2205/28 , C09D11/32 , C09D11/322
摘要： A recording medium containing a substantially colorless compound in which at least 10 atoms having conjugate π electrons are present on a per-molecule basis, wherein it is especially preferable that the compound has at least two aromatic ring groups and/or shows no fluorescence. An ink composition used for printing in image form on media, with the composition containing a dye and controlling a hue change caused in the printed images over a period of one hour immediately after the printing to 5 or below in color-difference terms. And a method of recording images on media by printing an ink composition in image form, wherein the ink composition contains a dye and a hue change caused in the printed images over a period of one hour immediately after the printing is controlled to 5 or below in color-difference terms.
摘要翻译：含有基本上无色的化合物的记录介质，其中至少10个具有共轭键的原子; 电子在每个分子的基础上存在，其中特别优选该化合物具有至少两个芳环基和/或不显示荧光。用于在介质上以图像形式印刷的油墨组合物，其组合物含有染料，并且在印刷后立即将印刷图像中的色调变化控制在5或更低的色差条件下。以及通过以图像形式印刷油墨组合物来在介质上记录图像的方法，其中在打印被控制到5或更低之后，油墨组合物在短时间内将打印图像中的染料和色调变化在1小时内引起色差项。

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