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1. 发明授权

US09361267B2 Splitable and scalable normalizer for vector data 有权
公开(公告)号：US09361267B2
公开(公告)日：2016-06-07
申请号：US14016607
申请日：2013-09-03
申请人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F15/78 , G06F15/80
CPC分类号： G06F7/49936 , G06F7/00 , G06F7/483 , G06F7/49915 , G06F9/30014 , G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F15/78 , G06F15/8053 , G06F2207/382
摘要： A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

2. 发明授权

US08949575B2 Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency 有权
公开(公告)号：US08949575B2
公开(公告)日：2015-02-03
申请号：US13326249
申请日：2011-12-14
申请人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Jens Leenstra , Silvia M. Mueller
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Jens Leenstra , Silvia M. Mueller
IPC分类号： G06F9/38 , G06F9/30 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/345 , G06F9/38 , G06F9/3826 , G06F9/3867 , G06F9/3869 , G06F15/76 , G06F15/8053
摘要： Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.

3. 发明申请

US20150067298A1 SPLITABLE AND SCALABLE NORMALIZER FOR VECTOR DATA 有权
标题翻译：用于矢量数据的可分离和可扩展的标准化
公开(公告)号：US20150067298A1
公开(公告)日：2015-03-05
申请号：US14016607
申请日：2013-09-03
申请人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F15/78
CPC分类号： G06F7/49936 , G06F7/00 , G06F7/483 , G06F7/49915 , G06F9/30014 , G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F15/78 , G06F15/8053 , G06F2207/382
摘要： A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.
摘要翻译：配置为支持标量数据路径中的向量操作的硬件电路组件。硬件电路组件被配置为以矢量模式配置和标量模式配置操作。硬件电路组件被配置为将标量模式配置分解为向量模式配置的左半部分和右半部分。硬件电路组件被配置为在矢量模式配置中的一个或多个互连多路复用器级上执行一个或多个位移位。硬件电路组件被配置为在位向量模式配置的左半部分和右半部分接收数据的比特位置包括复制的粗略移位复用器，从而产生一个或多个共享比特位置的粗移位复用器。

4. 发明申请

US20130159666A1 REDUCING ISSUE-TO-ISSUE LATENCY BY REVERSING PROCESSING ORDER IN HALF-PUMPED SIMD EXECUTION UNITS 有权
标题翻译：通过在半导体SIMD执行单元中反转加工订单减少发行问题的延迟
公开(公告)号：US20130159666A1
公开(公告)日：2013-06-20
申请号：US13326249
申请日：2011-12-14
申请人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Jens Leenstra , Silvia M. Mueller
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Jens Leenstra , Silvia M. Mueller
IPC分类号： G06F9/38 , G06F9/345 , G06F15/76 , G06F9/312
CPC分类号： G06F9/30036 , G06F9/345 , G06F9/38 , G06F9/3826 , G06F9/3867 , G06F9/3869 , G06F15/76 , G06F15/8053
摘要： Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.
摘要翻译：描述了通过反转半抽头单指令多数据（SIMD）执行单元中的处理顺序来减少发出问题的延迟的技术。在一个实施例中，提供了一种处理器功能单元，其包括前端单元和执行核心单元，后端单元，执行顺序控制信号单元，耦合在其中并且输出之间的第一互连和执行核心单元的输入以及耦合的第二互连在后端单元的输出和前端单元的输入之间。在操作中，执行顺序控制信号单元在接收到第一向量指令时基于所施加的时钟信号的奇偶校验产生转发顺序控制信号。该控制信号又用于经由互连选择性地转发第一向量指令的执行结果的第一和第二部分，以用于依赖的第二向量指令的执行。

5. 发明授权

US09122517B2 Fused multiply-adder with booth-encoding 有权
标题翻译：融合式加法器与展位编码
公开(公告)号：US09122517B2
公开(公告)日：2015-09-01
申请号：US13493002
申请日：2012-06-11
申请人： Maarten J. Boersma , Klaus Michael Kroener , Christophe J. Layer , Silvia M. Mueller
发明人： Maarten J. Boersma , Klaus Michael Kroener , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F7/483 , G06F7/53 , G06F7/544 , G06F7/509 , G06F7/533
CPC分类号： G06F7/483 , G06F7/509 , G06F7/5324 , G06F7/5332 , G06F7/5443
摘要： A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
摘要翻译：公开了一种融合乘法器。融合乘法加法器包括布斯编码器，分数乘法器，进位校正器和加法器。 Booth编码器最初编码第一个操作数。分数乘法器将布斯特编码的第一操作数乘以第二操作数以产生部分乘积，然后将部分乘积减少为一组冗余和和携带向量。进位校正器然后产生用于校正进位矢量的进位校正因子。加法器将冗余和并将载入和进位校正因子加到第三个操作数，以产生最终结果。

6. 发明申请

US20130332501A1 Fused Multiply-Adder with Booth-Encoding 有权
标题翻译：融合乘法加码器与展位编码
公开(公告)号：US20130332501A1
公开(公告)日：2013-12-12
申请号：US13493002
申请日：2012-06-11
申请人： Maarten J. Boersma , Klaus Michael Kroener , Christophe J. Layer , Silvia M. Mueller
发明人： Maarten J. Boersma , Klaus Michael Kroener , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F7/44 , G06F7/42
CPC分类号： G06F7/483 , G06F7/509 , G06F7/5324 , G06F7/5332 , G06F7/5443
摘要： A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
摘要翻译：公开了一种融合乘法器。融合乘法加法器包括布斯编码器，分数乘法器，进位校正器和加法器。 Booth编码器最初编码第一个操作数。分数乘法器将布斯特编码的第一操作数乘以第二操作数以产生部分乘积，然后将部分乘积减少为一组冗余和和携带向量。进位校正器然后产生用于校正进位矢量的进位校正因子。加法器将冗余和并将载入和进位校正因子加到第三个操作数，以产生最终结果。

7. 发明申请

US20130124588A1 ENCODING DENSELY PACKED DECIMALS 有权
标题翻译：编码密封包装十进制
公开(公告)号：US20130124588A1
公开(公告)日：2013-05-16
申请号：US13296273
申请日：2011-11-15
申请人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
发明人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
IPC分类号： G06F7/483
CPC分类号： G06F7/491 , G06F7/49915 , G06F2207/4911 , G06F2207/4912
摘要： According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.
摘要翻译：根据本公开的一个方面，公开了一种用于编码密集包装小数的方法和技术。该方法包括：执行被配置为以二进制编码十进制（BCD）格式对十进制数据执行浮点运算的浮点指令; 确定所述操作的结果是否包括舍入尾数溢出; 并且响应于确定所述操作的结果包括四舍五入的尾数溢出，通过将所述BCD格式化的十进制数据的所述BCD格式的十进制数据的选择位值移位，以密集的十进制（DPD）格式将所述操作的结果压缩为十进制数据十进制数据以一位数字选择DPD格式的位位置。

8. 发明授权

US09128758B2 Encoding densely packed decimals 有权
标题翻译：编码密集的小数
公开(公告)号：US09128758B2
公开(公告)日：2015-09-08
申请号：US13296273
申请日：2011-11-15
申请人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
发明人： Michael K. Kroener , Christophe J. Layer , Petra Leber , Silvia M. Mueller
IPC分类号： G06F7/491 , G06F7/499
CPC分类号： G06F7/491 , G06F7/49915 , G06F2207/4911 , G06F2207/4912
摘要： According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.
摘要翻译：根据本公开的一个方面，公开了一种用于编码密集包装小数的方法和技术。该方法包括：执行被配置为以二进制编码十进制（BCD）格式对十进制数据执行浮点运算的浮点指令; 确定所述操作的结果是否包括舍入尾数溢出; 并且响应于确定所述操作的结果包括四舍五入的尾数溢出，通过将所述BCD格式化的十进制数据的所述BCD格式的十进制数据的选择位值移位，以密集的十进制（DPD）格式将所述操作的结果压缩为十进制数据十进制数据以一位数字选择DPD格式的位位置。

9. 发明申请

US20130173681A1 Range Check Based Lookup Tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US20130173681A1
公开(公告)日：2013-07-04
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F1/035 , G06F12/00 , G06F7/487
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路对边界单元值子集中的每个边界单元值进行第二值的比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

10. 发明授权

US08954485B2 Range check based lookup tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US08954485B2
公开(公告)日：2015-02-10
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38 , G06F7/44
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

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