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1. 发明申请

WO2011075316A1 METHOD AND APPARATUS FOR DISPLAYING INFORMATION IN AN ELECTRONIC DEVICE 审中-公开
标题翻译：用于在电子设备中显示信息的方法和装置
公开(公告)号：WO2011075316A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/058671
申请日：2010-12-02
申请人： MOTOROLA MOBILITY, INC. , WANG, Geng , FOLEY, Sheila, A. , POWELL, Ryan, A.
发明人： WANG, Geng , FOLEY, Sheila, A. , POWELL, Ryan, A.
IPC分类号： G06F3/048
CPC分类号： G06F3/0485 , G06F3/0483 , G06F3/04883 , G06F2203/04803 , G06F2203/04806
摘要： A method and apparatus includes an electronic device that displays (110) a plurality of members on a first portion of a display and receives (115) a first input on the first portion of the display, wherein the input selects a first member from the plurality of members. Then, the electronic device enlarges (120) the first member and displays (130) additional information associated with the first member on the first portion of the display. After the selection, the device determines (135) if the received input is an entry input. If the input is determined to be an entry input, then detailed information associated with the first member is displayed (140) on a second portion of the display.
摘要翻译：一种方法和装置包括：电子设备，其在显示器的第一部分上显示（110）多个构件，并且在所述显示器的第一部分上接收（115）第一输入，其中所述输入从所述多个的成员。然后，电子设备放大（120）第一构件，并在显示器的第一部分上显示（130）与第一构件相关联的附加信息。在选择之后，设备确定（135）接收到的输入是否是入口输入。如果输入被确定为输入输入，则在显示器的第二部分上显示与第一成员相关联的详细信息（140）。

2. 发明申请

WO2011079187A1 NETWORK COPOLYMER CROSSLINKED COMPOSITIONS AND PRODUCTS COMPRISING THE SAME 审中-公开
标题翻译：网络共聚物交联组合物和包含该组合物的产品
公开(公告)号：WO2011079187A1
公开(公告)日：2011-06-30
申请号：PCT/US2010/061767
申请日：2010-12-22
申请人： MOMENTIVE PERFORMANCE MATERIALS INC. , LU, Ning , GONZALEZ, Sigfredo , SILVESTRE, Emie, M. , WANG, Geng
发明人： LU, Ning , GONZALEZ, Sigfredo , SILVESTRE, Emie, M. , WANG, Geng
IPC分类号： C09D4/00
CPC分类号： C09D4/00
摘要： The present invention provides for a household, agricultural, coating or personal care product composition containing the crosslinked reaction product of a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH 2 =C(R 3 )C(O)OX a (C 2 H 4 O) b (C 3 H 6 O) c (C 4 H 8 O) d ]pP(O)(OY) q (OZ) r where R 3 = H or alkyl of 1 to about 6 carbon atoms; X= alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100;b is 0 to about 100;c is 0 to about 100; d is 0 to about 100;q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p +q +r = 3; and Y and Z is H, or metal ion; and CH 2 =C(R 3 )C(O)OX a' (C 2 H 4 O) b' (C 3 H 6 O) c' (C 4 H 8 O) d' -SO 3 -Y) where R 3 = H or alkyl of from 1 to about 6 carbon atoms; X= alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a' is 0 to about 100; b' is 0 to about 100; c' is 0 to about 100; d' is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).
摘要翻译：本发明提供一种家用，农业，涂料或个人护理产品组合物，其含有网状组合物的交联反应产物，反应产物为：（i）至少一种阴离子可聚合烯属不饱和单体（I），其选自其中R 3 = H或1至约6个碳原子的烷基（CH 2 = C（R 3）C（O）O X a（C 2 H 4 O）b（C 3 H 6 O）c（C 4 H 8 O）d] ; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0至约100; b为0至约100; c为0至约100; d为0至约100; q为0至约2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; 和C 1 -C 6烷基;和C 1 -C 6烷基;和C 1 -C 6烷基，C 1 -C 6烷基， X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0〜100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

3. 发明申请

WO2011079012A1 NETWORK COPOLYMER CROSSLINKED COMPOSITIONS AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：网络共聚物交联组合物及其制备方法
公开(公告)号：WO2011079012A1
公开(公告)日：2011-06-30
申请号：PCT/US2010/060713
申请日：2010-12-16
申请人： MOMENTIVE PERFORMANCE MATERIALS INC. , LU, Ning , GONZALEZ, Sigfredo , SILVESTRE, Emie, M. , WANG, Geng
发明人： LU, Ning , GONZALEZ, Sigfredo , SILVESTRE, Emie, M. , WANG, Geng
IPC分类号： C08F230/02 , C08F220/38
CPC分类号： C08F220/38 , C08F228/02 , C08F230/02
摘要： The present invention is directed to a network composition having the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH 2 =C(R 3 )C(O)OX a (C 2 H 4 O) b (C 3 H 6 O) c ,(C 4 H 8 O) d ] p P(OY) a (OZ) r where R 3 = H or alkyl of 1 to about 6 carbon atoms; X= alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100;c is 0 to about 100; d is 0 to about 100;q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p +q +r=3; and Y and Z is H, or metal ion; and CH 2 =C(R 3 )C(O)OX 3 (C 2 H 4 O) b (C 3 H 6 O) c (C 4 H 8 O) d -SO 3 -Y) where R 3 = H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a' is 0 to about 100; b' is 0 to about 100; c' is 0 to about 100; d' is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III) capable of copolymerizing with (I) and (II).
摘要翻译：本发明涉及一种具有以下反应产物的网络组合物：（i）至少一种选自[CH2 = C（R3）C（O）OXa（C2H4O））的阴离子可聚合烯属不饱和单体（I） b（C 3 H 6 O）c，（C 4 H 8 O）d] pP（OY）a（OZ）r其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0〜100; b为0至约100; c为0至约100; d为0至约100; q为0至约2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; 和CH 2 = C（R 3）C（O）OX 3（C 2 H 4 O）b（C 3 H 6 O）c（C 4 H 8 O）d -SO 3 -Y）其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0至约100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

4. 发明申请

WO2004064148A1 HIGH PERFORMANCE EMBEDDED DRAM TECHNOLOGY WITH STRAINED SILICON 审中-公开
标题翻译：具有应变硅的高性能嵌入式DRAM技术
公开(公告)号：WO2004064148A1
公开(公告)日：2004-07-29
申请号：PCT/US2003/000562
申请日：2003-01-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , MANDELMAN, Jack, A. , GAMBINO, Jeffrey, P. , WANG, Geng
发明人： MANDELMAN, Jack, A. , GAMBINO, Jeffrey, P. , WANG, Geng
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3081 , H01L27/10864
摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.
摘要翻译：半导体器件制造在同一衬底的应变层区域和无应变层的层中。第一半导体器件，例如存储器单元，例如在衬底的无应变层的区域中形成深沟槽存储单元。在相同的衬底中选择性地形成应变层区域。第二半导体器件（66,68,70），例如FET，例如，一个MOSFET逻辑器件，形成在应变层区域中。

5. 发明申请

WO2013019305A1 EPITAXIAL EXTENSION CMOS TRANSISTOR 审中-公开
标题翻译：外延扩展CMOS晶体管
公开(公告)号：WO2013019305A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/040067
申请日：2012-05-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PEI, Chengwen , WANG, Geng , ZHANG, Yanli
发明人： PEI, Chengwen , WANG, Geng , ZHANG, Yanli
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth d 1 around a gate structure on the semiconductor layer, forming a disposable spacer 58 around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth d2 greater than the first depth d1. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region 16 and an integrated epitaxial drain and drain extension region 18. A replacement gate structure can be formed after deposition and of a planarization dielectric layer 70 and subsequent removal of the gate structure and laterally expand the gate cavity 59 over expitaxial source 16 and drain extension regions 18. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
摘要翻译：通过在半导体层上形成围绕栅极结构的第一深度d 1的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔件58以覆盖近端部分并且通过形成大于第一深度d1的第二深度d2的一对第二沟槽。去除一次性间隔物，并且进行选择性外延以形成集成的外延源和源极延伸区域16以及集成的外延漏极和漏极扩展区域18.可以在沉积之后形成替代栅极结构，并且可以在平坦化介电层70和随后去除栅极结构并且在外延源极16和漏极延伸区域18上横向膨胀栅极腔59.或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

6. 发明申请

WO2007082227A2 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：WO2007082227A2
公开(公告)日：2007-07-19
申请号：PCT/US2007/060317
申请日：2007-01-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHENG, Kangguo , DIVAKARUNI, Ramachandra , MANDELMAN, Jack, A. , RADENS, Carl, J. , WANG, Geng
发明人： CHENG, Kangguo , DIVAKARUNI, Ramachandra , MANDELMAN, Jack, A. , RADENS, Carl, J. , WANG, Geng
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括作为整体电容源连接在一起的多个电容器（102）。第一存取晶体管（104）耦合在所述多个电容器中的第一电容器和第一位线之间并且第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

7. 发明申请

WO2010091918A1 METHOD AND STRUCTURE FOR FORMING DEVICES ON THE FRONT SIDE AND CAPACITORS ON THE BACK SIDE OF A WAFER 审中-公开
标题翻译：在前置侧面和前端的电容器上形成设备的方法和结构
公开(公告)号：WO2010091918A1
公开(公告)日：2010-08-19
申请号：PCT/EP2010/050627
申请日：2010-01-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BOOTH, Roger, Allen, Jr. , CHENG, Kangguo , HANNON, Robert , TODI, Ravi , WANG, Geng
发明人： BOOTH, Roger, Allen, Jr. , CHENG, Kangguo , HANNON, Robert , TODI, Ravi , WANG, Geng
IPC分类号： H01L27/06 , H01L27/07 , H01L21/334 , H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L27/0605 , H01L27/0733 , H01L27/1203 , H01L28/90 , H01L29/66181
摘要： A method of forming a semiconductor structure includes providing a wafer (100). Devices (125) are formed on a front side of the wafer. A through-silicon-via (120) is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor (170) is formed in the deep trenches. The through-silicon-via connects the deep trench capacitor to the devices.
摘要翻译：形成半导体结构的方法包括提供晶片（100）。器件（125）形成在晶片的前侧。在晶片的基板上形成贯通硅通孔（120）。深沟槽形成在晶片的背面。在深沟槽中形成深沟槽电容器（170）。直通硅通孔将深沟槽电容器连接到器件。

8. 发明申请

WO2009053251A1 INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 审中-公开
标题翻译：多金属门工作功能结构的整合方案
公开(公告)号：WO2009053251A1
公开(公告)日：2009-04-30
申请号：PCT/EP2008/063533
申请日：2008-10-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHENG, Kangguo , CHUDZIK, Michael , DIVAKARUNI, Ramachandra , WANG, Geng , WONG, Robert , YANG, Haining
发明人： CHENG, Kangguo , CHUDZIK, Michael , DIVAKARUNI, Ramachandra , WANG, Geng , WONG, Robert , YANG, Haining
IPC分类号： H01L21/8238 , H01L21/8239 , H01L29/51 , H01L29/49 , H01L27/105
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

9. 发明申请

WO2007023011A3 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
公开(公告)号：WO2007023011A3
公开(公告)日：2007-03-01
申请号：PCT/EP2006/063581
申请日：2006-06-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MANDELMAN, Jack , CHENG, Kangguo , DIVAKARUNI, Ramachandra , RADENS, Carl , WANG, Geng
发明人： MANDELMAN, Jack , CHENG, Kangguo , DIVAKARUNI, Ramachandra , RADENS, Carl , WANG, Geng
IPC分类号： H01L27/108 , H01L21/8242
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

10. 发明申请

WO2011139872A1 ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 审中-公开
标题翻译： EDRAM的增强电容深度电容器
公开(公告)号：WO2011139872A1
公开(公告)日：2011-11-10
申请号：PCT/US2011/034430
申请日：2011-04-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KWON, Oh-Jung , LEE, Junedong , PEI, Chengwen , WANG, Geng
发明人： KWON, Oh-Jung , LEE, Junedong , PEI, Chengwen , WANG, Geng
IPC分类号： H01L29/94
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

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