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1. 发明申请

WO2014133768A2 CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING 审中-公开
标题翻译：用于均衡脉冲宽度调制时序的可配置时间延迟
公开(公告)号：WO2014133768A2
公开(公告)日：2014-09-04
申请号：PCT/US2014/016189
申请日：2014-02-13
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： KRIS, Bryan , DAY, John , DUMAIS, Alex , BOWLING, Stephen
IPC分类号： H02M1/32
CPC分类号： H03K5/133 , H02M1/08 , H02M1/32 , H02M1/38 , H02M3/3353 , H02M3/33576
摘要： A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.
摘要翻译：多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本上为零的延迟来实现。此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

2. 发明申请

WO2022081687A1 SYSTEM WITH INCREASING PROTECTED STORAGE AREA AND ERASE PROTECTION 审中-公开
公开(公告)号：WO2022081687A1
公开(公告)日：2022-04-21
申请号：PCT/US2021/054754
申请日：2021-10-13
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SAMUEL, Roshan , PFEIFER, Erick , DAY, John , UJVARI, Daniel
IPC分类号： G06F12/02 , G06F12/14 , G06F21/62 , G06F21/56 , G06F21/80
摘要： An apparatus may include a processor. The apparatus may include a memory communicatively coupled to the processor. The apparatus may include a memory control circuit (MCC). The MCC may be configured to define a protected portion of the memory, wherein the protected portion of the memory is configured for read-only access by the processor, increase a size of the protected portion of the memory, and, after the increase in size of the protected portion of the memory, prevent decreases of the size of the protected portion of the memory.

3. 发明公开

EP2965410A2 CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING 有权
标题翻译：配置的时间延误补偿脉冲宽度调制时序
公开(公告)号：EP2965410A2
公开(公告)日：2016-01-13
申请号：EP14708378.6
申请日：2014-02-13
申请人： Microchip Technology Incorporated
发明人： KRIS, Bryan , DAY, John , DUMAIS, Alex , BOWLING, Stephen
IPC分类号： H02M1/32 , H02M1/38 , H02M1/08 , H02M3/335
CPC分类号： H03K5/133 , H02M1/08 , H02M1/32 , H02M1/38 , H02M3/3353 , H02M3/33576
摘要： A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

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