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1. 发明申请

US20020192918A1 Heterojunction bipolar transistor and method for fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US20020192918A1
公开(公告)日：2002-12-19
申请号：US10224468
申请日：2002-08-21
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Takeshi Takagi , Koichiro Yuki , Kenji Toyoda , Yoshihiko Kanzawa
IPC分类号： H01L021/331
CPC分类号： H01L29/7378 , H01L29/161 , H01L29/66242
摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Gecontent is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.
摘要翻译：通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。通过使Si集电体层的SiGeC基底层中的晶格应变量为1.0％以下，带隙可以窄于常规实际SiGe（Gecontent约为10％）的带隙，并且具有良好的晶体可以在热处理后保持。结果，可以实现没有实际麻烦的窄带隙基。

2. 发明申请

US20020158313A1 Heterojunction bipolar transistor and method for fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US20020158313A1
公开(公告)日：2002-10-31
申请号：US10127579
申请日：2002-04-23
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Takeshi Takagi , Koichiro Yuki , Kenji Toyoda , Yoshihiko Kanzawa
IPC分类号： H01L027/082
CPC分类号： H01L29/7378 , H01L29/161 , H01L29/66242
摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.
摘要翻译：通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。通过使Si集电体层的SiGeC基底层的晶格应变量为1.0％以下，带隙可以窄于现有实际SiGe的带隙（Ge含量为10％左右），良好结晶可以在热处理后保持。结果，可以实现不具有实际不便的窄带隙基。

3. 发明申请

US20030008452A1 Semiconductor device and its fabrication method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20030008452A1
公开(公告)日：2003-01-09
申请号：US10188108
申请日：2002-07-03
申请人： Matsushita Electric Industrial Co., LTd.
发明人： Takeshi Takagi
IPC分类号： H01L021/8238
CPC分类号： H01L29/66651 , H01L21/76264 , H01L21/76283 , H01L29/41725 , H01L29/458 , H01L29/665 , H01L29/783 , H01L29/78615 , H01L29/78618 , H01L29/78639
摘要： A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.
摘要翻译：半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜漏区。因为源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。由此，能够实现高速运转，高集成化。

4. 发明申请

US20020135009A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20020135009A1
公开(公告)日：2002-09-26
申请号：US10061365
申请日：2002-02-04
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Teruhito Ohnishi , Takeshi Takagi , Akira Asai , Taizo Fujii , Mitsuo Sugiura , Yoshihisa Minami
IPC分类号： H01L027/108
CPC分类号： H01L29/93 , H01L27/0664 , H01L27/0808
摘要： A variable capacitor includes an Nnull layer including a variable capacitance region, a Pnull layer epitaxially grown on the Nnull layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the Nnull layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the Pnull layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the Nnull layer, reduction in variation range of the capacitance can be suppressed.
摘要翻译：可变电容器包括包含可变电容区域的N +层，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（杂双相晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与可变电容器的P +层同时外延生长的Si / SiGe层。由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

5. 发明申请

US20040259319A1 Semiconductor device and process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20040259319A1
公开(公告)日：2004-12-23
申请号：US10891038
申请日：2004-07-15
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
IPC分类号： H01L021/76
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76281 , H01L29/1054 , H01L29/66742 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
摘要翻译：本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

6. 发明申请

US20040142522A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20040142522A1
公开(公告)日：2004-07-22
申请号：US10752409
申请日：2004-01-07
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Akira Inoue , Akira Asai , Teruhito Ohnishi , Haruyuki Sorada , Yoshihiro Hara , Takeshi Takagi
IPC分类号： H01L021/336
CPC分类号： H01L29/66772 , H01L21/76895 , H01L29/783 , H01L29/78615 , H01L29/78621
摘要： A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.
摘要翻译：根据本发明的半导体器件及其制造方法是：在半导体衬底的预定区域上形成栅极绝缘体; 栅电极形成在栅极绝缘体上; 源极和漏极区域分别形成在预定区域的位于栅极电极的两侧的部分中; 由不同于所述源极和漏极区域的所述预定区域的区域形成的体区; 以及使所述栅电极和所述体区域电连接的触点，其中，与所述栅电极连接的所述触点的一部分在平面图中形成为与所述栅电极相交。

7. 发明申请

US20040094811A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20040094811A1
公开(公告)日：2004-05-20
申请号：US10657799
申请日：2003-09-09
申请人： Matsushita Electric Industrial Co., LTD
发明人： Takeshi Takagi
IPC分类号： H01L029/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L29/7782 , H01L29/802
摘要： A semiconductor device according to the invention includes: a semiconductor layer (10-15); a gate insulator (16) provided on the semiconductor layer; a gate electrode (17) provided on the gate insulator; a source region (20a) and a drain region (20b), which are of a first conductivity type and are provided in the semiconductor layer on both sides of the gate electrode in plan view; a cap layer (25), a channel region (24), and an under-channel region (23,22), which are of a second conductivity type and are provided in the semiconductor layer between the source region and the drain region in a descending order from an interface with the gate insulator; and a bias electrode member (Vbs) for applying a voltage to the under-channel region, wherein the channel region is formed of a first semiconductor, the cap layer and the under-channel region are formed of a second semiconductor and a third semiconductor, respectively, each of which has a larger band gap than the first semiconductor, the bias electrode member is capable of applying the voltage independently of the gate electrode.
摘要翻译：根据本发明的半导体器件包括：半导体层（10-15）; 设置在所述半导体层上的栅极绝缘体（16）设置在栅极绝缘体上的栅电极（17）源极区域（20a）和漏极区域（20b），它们是第一导电类型，并且在平面图中设置在栅电极两侧的半导体层中; 具有第二导电类型的盖层（25），沟道区（24）和下沟道区（23,22），并且设置在源区和漏区之间的半导体层中从与栅极绝缘体的界面降序; 以及用于向下通道区域施加电压的偏置电极部件（Vbs），其中所述沟道区域由第一半导体形成，所述覆盖层和所述下部沟道区域由第二半导体和第三半导体形成，分别具有比第一半导体更大的带隙，偏置电极构件能够独立于栅电极施加电压。

8. 发明申请

US20040251473A1 Bipolar transistor and fabrication method thereof 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20040251473A1
公开(公告)日：2004-12-16
申请号：US10882220
申请日：2004-07-02
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Akira Asai , Teruhito Ohnishi , Takeshi Takagi
IPC分类号： H01L031/0328
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/36 , H01L29/7378 , Y10S438/936
摘要： A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a Pnull polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.
摘要翻译：通过在Si衬底上的集电极层102上的外延生长，顺序地生长SiGe间隔层151，包括硼的梯度SiGe基极层152和Si覆盖层153。在Si覆盖层153上形成第二沉积氧化物膜112，该第二沉积氧化物膜112具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115，形成发射极扩散层153a 通过将磷扩散到Si覆盖层153中。当Si覆盖层153生长时，通过原位掺杂使Si覆盖层153仅在其上部包含硼，则耗尽层的宽度 154变窄，并且复合电流降低，从而可以提高电流特性的线性。

9. 发明申请

US20030201497A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20030201497A1
公开(公告)日：2003-10-30
申请号：US10370766
申请日：2003-02-24
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
IPC分类号： H01L021/8238 , H01L027/148 , H01L029/768 , H01L031/062
CPC分类号： H01L29/802 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/10873 , H01L27/11502 , H01L27/11507 , H01L27/1203 , H01L27/1214 , H01L27/1222 , H01L28/55 , H01L29/1054 , H01L29/783 , H01L29/78687
摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
摘要翻译：在Si衬底101上依次沉积氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。将Si衬底101放置在室106中，以便将PZT膜105x照射 EHF波108.用EHF波的照射局部加热诸如PZT膜的电介质膜。结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

10. 发明申请

US20030052348A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20030052348A1
公开(公告)日：2003-03-20
申请号：US10268905
申请日：2002-10-11
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Takeshi Takagi , Akira Inoue
IPC分类号： H01L029/94
CPC分类号： H01L29/1054 , H01L21/84 , H01L27/1203 , H01L29/161 , H01L29/165 , H01L29/7782 , H01L29/783 , H01L29/78615 , H01L29/78648 , H01L29/78687
摘要： A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an nnull Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.
摘要翻译： HDTMOS包括Si衬底，掩埋氧化物膜和半导体层。半导体层包括上硅膜，外延生长的Si缓冲层，外延生长的SiGe膜和外延生长的Si膜。此外，HDTMOS包括n型高浓度Si体区域，n-Si区域，含有n型低浓度杂质的SiGe沟道区域，n型低浓度Si覆盖层和作为导体的接触体用于电连接栅电极和Si体区的构件。本发明通过在沟道层使用载流子行进的带边缘处的电位较小的材料，而不是构成体区的材料的情况下，使阈值电压保持较小。

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