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1. 发明申请

WO2015127207A1 METHOD AND APPARATUS FOR INCORPORATING PASSIVE DEVICES IN AN INTEGRATED PASSIVE DEVICE SEPARATE FROM A DIE 审中-公开
标题翻译：用于将被动装置并入被集成的被动装置中的方法和装置
公开(公告)号：WO2015127207A1
公开(公告)日：2015-08-27
申请号：PCT/US2015/016823
申请日：2015-02-20
申请人： MARVELL WORLD TRADE LTD. , LEONG, Poh Boon , WU, Albert , WANG, Long-Ching , SUTARDJA, Sehat
发明人： LEONG, Poh Boon , WU, Albert , WANG, Long-Ching , SUTARDJA, Sehat
IPC分类号： H01L23/66 , H01L25/16 , H01L49/02
CPC分类号： H04B1/40 , H01L21/76898 , H01L23/481 , H01L23/49503 , H01L23/49575 , H01L23/645 , H01L23/66 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/16 , H01L25/162 , H01L25/50 , H01L28/10 , H01L2223/6644 , H01L2223/6672 , H01L2223/6677 , H01L2224/16145 , H01L2224/16225 , H01L2224/16265 , H01L2224/32145 , H01L2224/32265 , H01L2224/48247 , H01L2224/48465 , H01L2224/49 , H01L2224/73204 , H01L2224/85 , H01L2924/00014 , H01L2924/102 , H01L2924/10253 , H01L2924/1304 , H01L2924/13091 , H01L2924/1421 , H01L2924/19011 , H01L2924/19103 , H04B1/00 , H04B15/04 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.
摘要翻译：包括第一管芯，集成无源器件和第二层的电路。第一管芯包括第一衬底和有源器件。集成无源器件包括第一层，第二衬底和无源器件。第二衬底包括通孔。无源器件至少在第一层或第二基板上实现。第二基板的每单位面积的电阻率大于第一基板的每单位面积的电阻率。第二层设置在第一管芯和集成无源器件之间。第二层包括支柱。每个支柱将相应的一个有源器件连接到（i）过孔中的一个，或（ii）无源器件中的一个。第一管芯，集成无源器件和第二层相对于彼此设置以形成堆叠。

2. 发明申请

WO2015120061A1 METHOD AND APPARATUS FOR IMPROVING THE RELIABILITY OF A CONNECTION TO A VIA IN A SUBSTRATE 审中-公开
标题翻译：用于改善与衬底相通的可靠性的方法和装置
公开(公告)号：WO2015120061A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/014477
申请日：2015-02-04
申请人： MARVELL WORLD TRADE LTD. , WANG, Long-Ching , WU, Albert , WU, Scott
发明人： WANG, Long-Ching , WU, Albert , WU, Scott
IPC分类号： H01L23/13 , H01L23/498
CPC分类号： H01L23/49827 , H01L21/4853 , H01L21/486 , H01L23/13 , H01L23/49811 , H01L23/49866 , H01L2224/11 , H05K1/0306 , H05K1/115 , H05K1/181 , H05K2201/09563 , H05K2201/10242 , H05K2201/10378 , Y10T29/49165
摘要： Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs.
摘要翻译：本公开的一些实施例提供一种半导体封装插入器，其包括具有第一表面和第二表面的衬底，在衬底的第一表面和第二表面之间延伸的多个通孔，多个通孔电连接电连接器或基板的第一表面上的电路到基板的第二表面上的电连接器或电路，以及至少部分地填充多个通孔的金属插塞。（i）第一表面或（ii）衬底的第二表面中的至少一个包括在金属插塞的远端处的凹陷。

3. 发明申请

WO2014026034A1 METHODS OF MAKING PACKAGES USING THIN CU FOIL SUPPORTED BY CARRIER CU FOIL 审中-公开
标题翻译：使用由运输公司支持的薄煎饼制作包装的方法
公开(公告)号：WO2014026034A1
公开(公告)日：2014-02-13
申请号：PCT/US2013/054192
申请日：2013-08-08
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Sehat , WU, Albert , SHIN, Hyun, J.
发明人： SUTARDJA, Sehat , WU, Albert , SHIN, Hyun, J.
IPC分类号： H01L21/48 , H01L23/31
CPC分类号： H05K3/007 , H01L21/4832 , H01L21/568 , H01L23/3107 , H01L2224/32245 , H01L2224/4809 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H05K1/182 , Y10T29/49146 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.
摘要翻译：在一个实施例中，提供了一种创建封装的方法，所述方法包括：提供初始衬底，其中所述初始衬底包括载体箔，功能铜箔以及所述载体箔和所述功能性铜之间的界面剥离层挫败; 在功能铜箔上堆积铜部分; 将芯片附接到第一铜部分; 将所述芯片耦合到第二铜部分; 至少用模具封装芯片和铜部分; 并移除载体箔和界面释放层。

4. 发明申请

WO2012054711A2 POWER/GROUND LAYOUT FOR CHIPS 审中-公开
标题翻译：电源/接地布局
公开(公告)号：WO2012054711A2
公开(公告)日：2012-04-26
申请号：PCT/US2011/057069
申请日：2011-10-20
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Sehat , HAN, Chung, Chyung , LI, Weidan , YU, Shuhua , CHENG, Chuan-cheng , WU, Albert
发明人： SUTARDJA, Sehat , HAN, Chung, Chyung , LI, Weidan , YU, Shuhua , CHENG, Chuan-cheng , WU, Albert
IPC分类号： H01L23/522
CPC分类号： H01L21/76885 , H01L23/3107 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/061 , H01L2224/16145 , H01L2224/16245 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/731 , H01L2224/85 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
摘要翻译：本公开的实施例提供一种芯片，其包括形成在第一半导体管芯上的基底金属层和形成在基底金属层上的第一金属层。第一金属层包括被配置为路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛。芯片还包括形成在第一金属层上的第二金属层。第二金属层包括被配置为路由（i）接地信号或（ii）芯片中的功率信号中的至少一个的多个岛。

5. 发明申请

WO2011087798A1 PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：具有半导体基板的封装组件
公开(公告)号：WO2011087798A1
公开(公告)日：2011-07-21
申请号：PCT/US2010/061630
申请日：2010-12-21
申请人： MARVELL WORLD TRADE LTD. , LIOU, Shiann-Ming , SUTARDJA, Sehat , WU, Albert , CHENG, Chuan-Cheng , WEI, Chien-Chuan
发明人： LIOU, Shiann-Ming , SUTARDJA, Sehat , WU, Albert , CHENG, Chuan-Cheng , WEI, Chien-Chuan
IPC分类号： H01L23/14 , H01L23/498 , H01L23/60 , H01L25/065
CPC分类号： H01L23/42 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/60 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上，半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。可以描述和/或要求保护其他实施例。

6. 发明申请

WO2009012122A1 METHOD FOR SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：低温分离方法
公开(公告)号：WO2009012122A1
公开(公告)日：2009-01-22
申请号：PCT/US2008/069704
申请日：2008-07-10
申请人： MARVELL WORLD TRADE LTD. , WU, Albert , CHANG, Runzi
发明人： WU, Albert , CHANG, Runzi
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/30608 , H01L21/3083 , H01L21/76232
摘要： Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.
摘要翻译：本文描述了用于使浅沟槽隔离结构的底角倒圆的方法。本发明的实施方案提供了一种方法，包括在基板的开口的侧壁上形成第一掩模层，在其第一掩蔽层的开口的底表面处移除第一深度到基板的第一部分在所述开口中的所述第一掩蔽层上形成第二掩蔽层，以及在所述第一和第二掩蔽层的所述开口的底表面处，将所述基板的第二部分移除到第二深度。还描述了其它实施例。

7. 发明申请

WO2007146307A3 STACK DIE PACKAGES 审中-公开
公开(公告)号：WO2007146307A3
公开(公告)日：2007-12-21
申请号：PCT/US2007/013821
申请日：2007-06-13
申请人： MARVELL WORLD TRADE LTD. , WU, Albert , KAO, Huahung
发明人： WU, Albert , KAO, Huahung
IPC分类号： H01L25/065
摘要： Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.

8. 发明申请

WO2011097089A2 RECESSED SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：凹陷的半导体基板
公开(公告)号：WO2011097089A2
公开(公告)日：2011-08-11
申请号：PCT/US2011/022370
申请日：2011-01-25
申请人： MARVELL WORLD TRADE LTD. , WU, Albert , CHEN, Roawen , HAN, Chung, Chyung , LIOU, Shiann-Ming , WEI, Chien-Chuan , CHANG, Runzi , WU, Scott , CHENG, Chuan-Cheng
发明人： WU, Albert , CHEN, Roawen , HAN, Chung, Chyung , LIOU, Shiann-Ming , WEI, Chien-Chuan , CHANG, Runzi , WU, Scott , CHENG, Chuan-Cheng
IPC分类号： H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供一种装置，其包括具有第一表面，与第一表面相对设置的第二表面的半导体衬底，其中第一表面的至少一部分凹陷以形成半导体衬底的凹入区域以及形成在半导体衬底的凹入区域中以提供半导体衬底的第一表面和第二表面之间的电或热通路的一个或多个通孔以及耦合到半导体衬底的管芯，管芯电耦合到在半导体衬底的凹陷区域中形成的一个或多个通孔。其他实施例可以被描述和/或要求保护。

9. 发明申请

WO2008124444A1 METHODS TO FORM WIDE HEATER TRENCHES AND TO FORM MEMORY CELLS TO ENGAGE HEATERS 审中-公开
标题翻译：形成宽加热器的方法和形成记忆细胞进入加热器的方法
公开(公告)号：WO2008124444A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/059148
申请日：2008-04-02
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , WEI, Chien-Chuan , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , WEI, Chien-Chuan , LEE, Winston , LEE, Peter
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Embodiments of the present invention, provide a method that includes providing a wafer including multiple cells, each cell including at least one emitter (108), and performing a lithographic operation on the wafer. The lithographic operation comprises forming heater trenches adjacent the emitters, each heater trench having a width' that extends over at least respective portions of two cells. Embodiments of the present invention also provide a method that includes providing wafer including multiple cells, each cell including at least -one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element (402a, 402b) adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极（108），并对所述晶片进行光刻操作。光刻操作包括在发射器附近形成加热器沟槽，每个加热器沟槽具有在两个单元的至少相应部分上延伸的宽度。本发明的实施例还提供了一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预先加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成与每个发射器相邻的加热器元件（402a，402b）。还描述了其它实施例。

10. 发明申请

WO2008097910A2 PHASE CHANGE MATERIAL (PCM) MEMORY DEVICES WITH BIPOLAR JUNCTION TRANSISTORS AND METHODS FOR MAKING THEREOF 审中-公开
标题翻译：具有双极结型晶体管的相变材料（PCM）存储器件及其制造方法
公开(公告)号：WO2008097910A2
公开(公告)日：2008-08-14
申请号：PCT/US2008/052924
申请日：2008-02-04
申请人： MARVELL WORLD TRADE LTD. , WU, Albert , WEI, Chien-Chuan , SWITZER, Roger
发明人： WU, Albert , WEI, Chien-Chuan , SWITZER, Roger
IPC分类号： H01L27/24
CPC分类号： H01L45/144 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675
摘要： Methods for fabricating highly compact PCM memory devices are described herein. The methods may include forming a bipolar junction transistor (BJT) structure on a substrate including creating a base of the BJT structure on the substrate and creating an emitter of the BJT structure on top of the base opposite of the substrate. A heating element may then be constructed on the emitter of the BJT structure, wherein the heating element includes a material to generate heat when provided with an electrical current from the emitter. A phase change material (PCM) cell may then be built on the heating element opposite of the BJT structure.
摘要翻译：这里描述了用于制造高度紧凑的PCM存储器件的方法。该方法可以包括在衬底上形成双极结型晶体管（BJT）结构，包括在衬底上创建BJT结构的基底并且在与衬底相对的基底的顶部上创建BJT结构的发射极。然后可以在BJT结构的发射极上构造加热元件，其中加热元件包括在被提供来自发射极的电流时产生热量的材料。然后可以在与BJT结构相对的加热元件上构建相变材料（PCM）单元。

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