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1. 发明授权

US06233690B1 Mechanism for saving power on long latency stalls 有权
标题翻译：节省长时间延迟停电的机制
公开(公告)号：US06233690B1
公开(公告)日：2001-05-15
申请号：US09156552
申请日：1998-09-17
申请人： Lynn Choi , Harshvardhan Sharangpani
发明人： Lynn Choi , Harshvardhan Sharangpani
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3225 , G06F1/3237 , G06F1/3287 , G06F9/3824 , G06F9/3838 , G06F9/3857 , Y02D10/128 , Y02D10/171
摘要： A method for gating a clock signal to an execution unit on long latency memory stalls monitors a stall signal, a scoreboard (data) hazard signal, a resource hazard signal, and a data return signal. The clock signal is decoupled from the execution unit when the stall and data hazard signals are asserted for a selected interval and the data return and resource hazard signals are not asserted for a selected interval.
摘要翻译：在长时间延迟存储器停止时，将时钟信号选通到执行单元的方法监视失速信号，记分板（数据）危险信号，资源危险信号和数据返回信号。当停机和数据危险信号被断言一段选定的时间间隔时，时钟信号与执行单元去耦，并且数据返回和资源危险信号在所选时间间隔内不被断言。

2. 发明授权

US06240510B1 System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions 失效
标题翻译：用于处理指令集的系统，其中指令被发布给具有根据与指令集相关联的模板的优先顺序的执行单元
公开(公告)号：US06240510B1
公开(公告)日：2001-05-29
申请号：US09130387
申请日：1998-08-06
申请人： Tse-Yu Yeh , Harshvardhan Sharangpani , Michael Paul Corwin , Sujat Jamil
发明人： Tse-Yu Yeh , Harshvardhan Sharangpani , Michael Paul Corwin , Sujat Jamil
IPC分类号： G06F915
CPC分类号： G06F9/3885 , G06F9/30094 , G06F9/325 , G06F9/3806 , G06F9/3844
摘要： A system is provided for processing concurrently one or more branch instructions in an instruction bundle. The system includes multiple branch execution pipelines, each capable of executing a branch instruction to determine a branch direction, target address, and any side effects. Linking logic receives the resolved branch information and identifies a first branch instruction in execution order for which the branch direction is taken.
摘要翻译：提供一种用于同时处理指令束中的一个或多个分支指令的系统。该系统包括多个分支执行流水线，每个分支执行流水线能够执行分支指令以确定分支方向，目标地址和任何副作用。链接逻辑接收解析的分支信息，并以执行分支方向的执行顺序识别第一分支指令。

3. 发明授权

US06178498B1 Storing predicted branch target address in different storage according to importance hint in branch prediction instruction 失效
标题翻译：根据分支预测指令的重要性提示将预测的分支目标地址存储在不同的存储器中
公开(公告)号：US06178498B1
公开(公告)日：2001-01-23
申请号：US08993450
申请日：1997-12-18
申请人： Harshvardhan Sharangpani , Kent Fielden
发明人： Harshvardhan Sharangpani , Kent Fielden
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/3005 , G06F9/3844 , G06F9/3846
摘要： A branch prediction instruction is provided that includes hint information for indicating a storage location for associated branch prediction information in a hierarchy of branch prediction storage structures. When the hint information is in a first state, branch prediction information is stored in a first structure that provides single cycle access to the stored information. When the hint information is in a second state, the branch prediction information is stored in a second structure that provides slower access to the stored information.
摘要翻译：提供了一种分支预测指令，其包括用于指示分支预测存储结构的层级中的相关联的分支预测信息的存储位置的提示信息。当提示信息处于第一状态时，分支预测信息被存储在提供对存储的信息的单周期访问的第一结构中。当提示信息处于第二状态时，分支预测信息被存储在提供对存储的信息的较慢访问的第二结构中。

4. 发明授权

US6154760A Instruction to normalize redundantly encoded floating point numbers 失效
标题翻译：对冗余编码的浮点数进行归一化的指令
公开(公告)号：US6154760A
公开(公告)日：2000-11-28
申请号：US562899
申请日：1995-11-27
申请人： Harshvardhan Sharangpani
发明人： Harshvardhan Sharangpani
IPC分类号： G06F5/01 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an exponent field and an explicit bit. The apparatus further comprises a circuit to normalize the floating point number when the explicit bit is not set and the exponent field has a first predetermined value identifying a redundant denormal encoding of the floating point number. Otherwise the encoding of the number is not changed by the circuit.
摘要翻译：本发明是使浮点数归一化的装置。该装置具有包括浮点数的第一存储区域。浮点数包括指数字段和显式位。所述装置还包括当所述显式位未被设置并且所述指数字段具有标识所述浮点数的冗余异常编码的第一预定值时对所述浮点数进行归一化的电路。否则电路的编码不会改变。

5. 发明授权

US5768169A Method and apparatus for improved processing of numeric applications in the presence of subnormal numbers in a computer system 失效
标题翻译：用于在计算机系统中存在次正规数的情况下改进数字应用处理的方法和装置
公开(公告)号：US5768169A
公开(公告)日：1998-06-16
申请号：US537007
申请日：1995-10-02
申请人： Harshvardhan Sharangpani
发明人： Harshvardhan Sharangpani
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F2207/3816
摘要： An apparatus for storing data in a computer memory, the number originating from one of a plurality of floating point data formats. Each data format from which the number originates has a first exponent bias and a minimum exponent value. The number has a first exponent and an unbiased exponent value, the unbiased exponent value equal to the difference between the first exponent and the first exponent bias. The number also has a sign and a significand. The apparatus for storing the number in computer memory consists of at least one sign bit and a significand having an explicit integer bit, the explicit integer bit having a first predetermined value when the number is normal and having a second predetermined value when the number is denormal. The apparatus also has a second exponent with a second exponent bias, the second exponent equal to the sum of the unbiased exponent value and the second exponent bias when the number is normal, the second exponent equal to the sum of the minimum exponent value and the second exponent bias when the number is denormal.
摘要翻译：一种用于将数据存储在计算机存储器中的装置，所述数据源自多个浮点数据格式之一。数字起始的每个数据格式具有第一指数偏差和最小指数值。该数字具有第一指数和无偏指数值，无偏指数值等于第一指数和第一指数偏差之间的差。这个数字也有一个标志和一个有意义的数字。用于存储计算机存储器中的数字的装置由至少一个符号位和具有明显整数位的有效位构成，当数字正常时，该显式整数位具有第一预定值，并且当数字为非正常时具有第二预定值。该装置还具有带有第二指数偏差的第二指数，当数字正常时，第二指数等于无偏指数值和第二指数偏差之和，第二指数等于最小指数值与第二个指数偏差，当数字是不正常的。

6. 发明授权

US06629232B1 Copied register files for data processors having many execution units 失效
标题翻译：具有多个执行单位的数据处理器的复制寄存器文件
公开(公告)号：US06629232B1
公开(公告)日：2003-09-30
申请号：US09609911
申请日：2000-07-03
申请人： Ken Arora , Harshvardhan Sharangpani , Rajiv Gupta
发明人： Ken Arora , Harshvardhan Sharangpani , Rajiv Gupta
IPC分类号： G06F1300
CPC分类号： G06F9/3012 , G06F9/30141 , G06F9/3885 , G06F9/3891
摘要： Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different groups of execution units can read from and write to their own copy of the file registers by a set of local read and write ports. All of the register-file copies are synchronized by writing data from the execution units to remote write ports in at least some registers in other copies of the register file. Each copy can be divided into local and global registers. While all copies of the global registers continue to be written by the remote write ports, the local registers can be written only by a local cluster of execution units. Alternatively or additionally, all of the execution units can write to their local register-file copy, but only some of the units can write the global registers in all copies of the register file.
摘要翻译：互连主导的大型寄存器文件在芯片面积和延迟时间上都有所减少。具有多个执行单元的处理器中的寄存器文件被分成多个副本。不同的执行单元组可以通过一组本地读写端口读取和写入其自己的文件寄存器副本。所有寄存器文件副本都通过将数据从执行单元写入到寄存器文件的其他副本的至少一些寄存器中的远程写入端口来同步。每个副本可分为本地和全局寄存器。虽然全局寄存器的所有副本仍然由远程写入端口写入，但本地寄存器只能由本地执行单元集群写入。或者或另外，所有执行单元都可以写入其本地寄存器文件副本，但只有一些单元可以将全局寄存器写入寄存器文件的所有副本。

7. 发明授权

US06591359B1 Speculative renaming of data-processor registers 有权
标题翻译：将虚拟寄存器规范映射到流水线处理器中的物理寄存器
公开(公告)号：US06591359B1
公开(公告)日：2003-07-08
申请号：US09223843
申请日：1998-12-31
申请人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
发明人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
IPC分类号： G06F934
CPC分类号： G06F9/3863 , G06F9/384 , G06F9/3842
摘要： A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.
摘要翻译：流水线数据处理器具有不同执行阶段的指令。一些指令将虚拟地址指定为具有物理地址的寄存器的文件。推测翻译器将一个流水线阶段的指令的虚拟寄存器映射到物理寄存器，以便在稍后的流水线阶段由指令进行投机使用。寄存器有多个不同的翻译区域。投机重命名失败恢复到重命名数据的归档副本。

8. 发明授权

US5922065A Processor utilizing a template field for encoding instruction sequences in a wide-word format 失效
标题翻译：处理器利用模板字段来编码宽字格式的指令序列
公开(公告)号：US5922065A
公开(公告)日：1999-07-13
申请号：US949279
申请日：1997-10-13
申请人： James M. Hull , Kent Fielden , Hans Mulden , Harshvardhan Sharangpani
发明人： James M. Hull , Kent Fielden , Hans Mulden , Harshvardhan Sharangpani
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30094 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/3853
摘要： A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.
摘要翻译：具有大寄存器文件的处理器利用模板字段来编码长指令字格式的一组最有用的指令序列。处理器的指令集包括作为多种不同指令类型之一的指令。处理器的执行单元类似地分类为不同类型，其中每个指令类型可以在一个或多个执行单元类型上执行。这些指令被分组在128位大小和对齐的容器中，称为捆绑包，每个包包括多个指令槽和模板字段，其指定指令槽与执行单元类型的映射。

9. 发明授权

US5848284A Method of transferring data between moderately coupled integer and floating point units 失效
标题翻译：中等耦合整数和浮点数之间传输数据的方法
公开(公告)号：US5848284A
公开(公告)日：1998-12-08
申请号：US563682
申请日：1995-11-28
申请人： Harshvardhan Sharangpani
发明人： Harshvardhan Sharangpani
IPC分类号： G06F9/315 , G06F9/38 , G06F15/16
CPC分类号： G06F9/30032 , G06F9/3885
摘要： A moderately coupled floating point and integer units of a processor allows for rapid transfer of data between the two units. The integer unit is comprised of a plurality of integer registers arranged into an integer register file and coupled to one or more integer execution units. Similarly, the floating point unit is comprised of a plurality of floating point registers arranged into a floating point register file and coupled to one or more floating point execution units. The two units operate as separate units except for the data transfer between them on a transfer bus. The transfer bus is the only direct data link between the two register files. Multiplexers are used to control the bit transfer between the two register files so that all or some of the bits of a register are transferred to a receiving register. Furthermore, the data transfer scheme allows for both numeric and Booleans to be transferred and compounding of Booleans can be performed in either numeric unit.
摘要翻译：处理器的适度耦合的浮点和整数单元允许在两个单元之间快速传输数据。整数单元由布置成整数寄存器文件并耦合到一个或多个整数执行单元的多个整数寄存器组成。类似地，浮点单元由布置在浮点寄存器堆中并耦合到一个或多个浮点执行单元的多个浮点寄存器组成。两个单元作为单独的单元操作，除了它们之间在传输总线上的数据传输。传输总线是两个寄存器文件之间唯一的直接数据链接。多路复用器用于控制两个寄存器文件之间的位传输，使寄存器的全部或部分位传送到接收寄存器。此外，数据传输方案允许数字和布尔传输，并且可以以数字单位执行布尔值的复合。

10. 发明授权

US06625693B2 Fast exception processing 有权
标题翻译：使用多个缓存处理程序进行快速异常处理
公开(公告)号：US06625693B2
公开(公告)日：2003-09-23
申请号：US09304372
申请日：1999-05-04
申请人： Ken Arora , Harshvardhan Sharangpani , Gary Hammond
发明人： Ken Arora , Harshvardhan Sharangpani , Gary Hammond
IPC分类号： G06F1200
CPC分类号： G06F9/3861
摘要： Fast exception processing is disclosed. In one embodiment, a system includes a splice cache, an exception logic, and an instrumentation mechanism. The splice cache contains one or more lightweight handlers. The exception logic is coupled to the splice cache and determines whether the corresponding lightweight handler for an exception is located in the splice cache. The instrumentation mechanism is coupled to the splice cache. The instrumentation mechanism inserts the lightweight handler into an execution stream.
摘要翻译：公开了快速异常处理。在一个实施例中，系统包括拼接高速缓存，异常逻辑和检测机制。拼接缓存包含一个或多个轻量级处理程序。异常逻辑耦合到拼接缓存，并确定对应于异常的轻量级处理程序是否位于拼接缓存中。仪器机制耦合到拼接缓存。仪器化机制将轻量级处理程序插入到执行流中。

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