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1. 发明授权

US06240510B1 System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions 失效
标题翻译：用于处理指令集的系统，其中指令被发布给具有根据与指令集相关联的模板的优先顺序的执行单元
公开(公告)号：US06240510B1
公开(公告)日：2001-05-29
申请号：US09130387
申请日：1998-08-06
申请人： Tse-Yu Yeh , Harshvardhan Sharangpani , Michael Paul Corwin , Sujat Jamil
发明人： Tse-Yu Yeh , Harshvardhan Sharangpani , Michael Paul Corwin , Sujat Jamil
IPC分类号： G06F915
CPC分类号： G06F9/3885 , G06F9/30094 , G06F9/325 , G06F9/3806 , G06F9/3844
摘要： A system is provided for processing concurrently one or more branch instructions in an instruction bundle. The system includes multiple branch execution pipelines, each capable of executing a branch instruction to determine a branch direction, target address, and any side effects. Linking logic receives the resolved branch information and identifies a first branch instruction in execution order for which the branch direction is taken.
摘要翻译：提供一种用于同时处理指令束中的一个或多个分支指令的系统。该系统包括多个分支执行流水线，每个分支执行流水线能够执行分支指令以确定分支方向，目标地址和任何副作用。链接逻辑接收解析的分支信息，并以执行分支方向的执行顺序识别第一分支指令。

2. 发明申请

US20050066153A1 Method for processing branch operations 审中-公开
标题翻译：处理分支操作的方法
公开(公告)号：US20050066153A1
公开(公告)日：2005-03-24
申请号：US10461782
申请日：2003-06-12
申请人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
发明人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
IPC分类号： G06F9/32 , G06F9/38 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/325 , G06F9/3844 , G06F9/3846
摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.
摘要翻译：使用分支预测指令和相关联的分支指令来处理分支操作。分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

3. 发明授权

US06611910B2 Method for processing branch operations 有权
标题翻译：处理分支操作的方法
公开(公告)号：US06611910B2
公开(公告)日：2003-08-26
申请号：US09169868
申请日：1998-10-12
申请人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent G. Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
发明人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent G. Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
IPC分类号： G06F930
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/325 , G06F9/3844 , G06F9/3846
摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.
摘要翻译：使用分支预测指令和相关联的分支指令来处理分支操作。分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

4. 发明授权

US06237077B1 Instruction template for efficient processing clustered branch instructions 失效
标题翻译：用于高效处理集群分支指令的指令模板
公开(公告)号：US06237077B1
公开(公告)日：2001-05-22
申请号：US08949277
申请日：1997-10-13
申请人： Harshvardhan Sharangpani , Michael Paul Corwin , Dale Morris , Kent Fielden , Tse-Yu Yeh , Hans Mulder , James Hull
发明人： Harshvardhan Sharangpani , Michael Paul Corwin , Dale Morris , Kent Fielden , Tse-Yu Yeh , Hans Mulder , James Hull
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/3853 , G06F9/3861
摘要： A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.
摘要翻译：提供了一种用于处理指令束中的一个或多个分支指令的方法。指令以捆绑中的执行顺序排序，分支指令在序列中最后排列。捆绑的指令被传送到与捆绑相关联的模板字段指示的执行单元。确定已解决的束的执行序列中的第一个分支指令，并且抑制执行序列中后续指令的退出。

5. 发明授权

US06304960B1 Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions 有权
标题翻译：通过比较预测和条件选择的暂定目标地址和分支条件的验证来验证群集中的分支的预测
公开(公告)号：US06304960B1
公开(公告)日：2001-10-16
申请号：US09130380
申请日：1998-08-06
申请人： Tse-Yu Yeh , Michael Paul Corwin , Judge K. Arora , Sujat Jamil , Sailesh Kottapalli
发明人： Tse-Yu Yeh , Michael Paul Corwin , Judge K. Arora , Sujat Jamil , Sailesh Kottapalli
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/322 , G06F9/325 , G06F9/3806 , G06F9/3842 , G06F9/3844 , G06F9/3861
摘要： A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines target addresses for the branches in the cluster. One of the determined target addresses is selected, using predicted branch directions. The selected target address is compared with a predicted target address, and resolved branch directions are compared with predicted branch directions. A misprediction is indicated if either comparison fails.
摘要翻译：用于验证分支指令簇的分支预测的系统包括地址验证模块和条件验证模块。地址验证模块确定集群中分支的目标地址。使用预测的分支方向选择确定的目标地址之一。将所选择的目标地址与预测的目标地址进行比较，并将分辨的分支方向与预测的分支方向进行比较。如果比较失败，则会显示错误预测。

6. 发明申请

US20120110392A1 MISALIGNMENT PREDICTOR 有权
标题翻译：失业预测者
公开(公告)号：US20120110392A1
公开(公告)日：2012-05-03
申请号：US13345260
申请日：2012-01-06
申请人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
发明人： Tse-Yu Yeh , Po-Yung Chang , Eric Hao
IPC分类号： G06F11/30
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/30145 , G06F9/3832 , G06F9/3861
摘要： In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
摘要翻译：在一个实施例中，处理器包括耦合以接收要在处理器中执行的存储器操作的指示的电路。电路被配置为预测存储器操作是否不对准。由处理器执行的执行存储器操作的多个访问取决于电路是否将存储器操作预测为未对准。在另一个实施例中，未对准预测器被耦合以接收存储器操作的指示，并且包括耦合到存储器的存储器和控制电路。存储器被配置为存储先前在处理器中执行期间被检测为未对准的存储器操作的多个指示。控制电路被配置为响应于所接收的指示与存储在存储器中的多个指示的比较来预测存储器操作是否失准。

7. 发明授权

US06282636B1 Decentralized exception processing system 有权
标题翻译：分散式异常处理系统
公开(公告)号：US06282636B1
公开(公告)日：2001-08-28
申请号：US09221197
申请日：1998-12-23
申请人： Tse-Yu Yeh , Gregory Mathews , Steven Tu
发明人： Tse-Yu Yeh , Gregory Mathews , Steven Tu
IPC分类号： G06F938
CPC分类号： G06F9/3861
摘要： A decentralized exception processing system includes a plurality of local exception units. Each local exception unit is coupled to process local exception signals from one or more processing resources that are proximate to it. Each local exception unit generates local commit signals, using order information for the instruction in an issue group and any local exception signals it receives. The local commit signals are combined to generate a global commit signal for each instruction in the issue group. Local exception signals are collected at a selected one of the local exception units and processed to generate a global exception unit. The selected local exception unit resteers control of the processing resources to an exception handler associated with the global exception unit.
摘要翻译：分散式异常处理系统包括多个局部异常单元。每个局部异常单元被耦合以处理来自其附近的一个或多个处理资源的局部异常信号。每个本地异常单元使用发布组中的指令的顺序信息和其接收的任何本地异常信号来生成本地提交信号。组合本地提交信号以为问题组中的每个指令生成全局提交信号。本地异常信号在选定的一个局部异常单元处收集，并被处理以产生全局异常单元。所选择的本地异常单元将处理资源的控制恢复到与全局异常单元相关联的异常处理器。

8. 发明授权

US06185676B2 Method and apparatus for performing early branch prediction in a microprocessor 失效
标题翻译：用于在微处理器中执行早期分支预测的方法和装置
公开(公告)号：US06185676B2
公开(公告)日：2001-02-06
申请号：US08940435
申请日：1997-09-30
申请人： Mitchell Alexander Poplingher , Carl Scafidi , Tse-Yu Yeh , Wenliang Chen
发明人： Mitchell Alexander Poplingher , Carl Scafidi , Tse-Yu Yeh , Wenliang Chen
IPC分类号： G06F1500
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A pipelined microprocessor having a branch prediction unit implemented in an instruction pointer generation stage of the microprocessor. The branch prediction unit includes a memory device having at least a first entry configured to hold at least a part of a memory address of a pre-selected branch instruction and at least a part of a memory address of a branch target corresponding to the pre-selected branch instruction. The branch prediction unit compares an instruction pointer of an instruction to be executed with the memory address of the pre-selected branch instruction. In response to a match between the instruction pointer and the memory address of pre-selected branch instruction, the unit causes the microprocessor to fetch an instruction corresponding to the branch target. In one embodiment, the instruction pointer generation stage of the microprocessor is implemented as a first stage of the pipelined microprocessor. In addition, the branch prediction unit is compares the instruction pointer and the memory address of the pre-selected branch instruction during a single clock cycle in which the instruction pointer is generated.
摘要翻译：具有在微处理器的指令指针生成级中实现的分支预测单元的流水线微处理器。分支预测单元包括具有至少第一条目的存储器件，其被配置为保持预选择的转移指令的存储器地址的至少一部分以及与预选择的转移指令对应的分支目标的存储器地址的至少一部分，选择分支指令。分支预测单元将要执行的指令的指令指针与预先选择的分支指令的存储器地址进行比较。响应于指令指针和预先选择的分支指令的存储器地址之间的匹配，单元使微处理器获取与分支目标相对应的指令。在一个实施例中，微处理器的指令指针生成级被实现为流水线微处理器的第一级。此外，分支预测单元在生成指令指针的单个时钟周期期间比较指令指针和预先选择的分支指令的存储器地址。

9. 发明授权

US6044456A Electronic system and method for maintaining synchronization of multiple front-end pipelines 失效
标题翻译：用于保持多个前端管道同步的电子系统和方法
公开(公告)号：US6044456A
公开(公告)日：2000-03-28
申请号：US002774
申请日：1998-01-05
申请人： Keshavram N. Murty , Nazar A. Zaidi , Darshana S. Shah , Tse-Yu Yeh
发明人： Keshavram N. Murty , Nazar A. Zaidi , Darshana S. Shah , Tse-Yu Yeh
IPC分类号： G06F9/38
CPC分类号： G06F9/3869
摘要： A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.
摘要翻译：描述了一种用于维持通过并行操作的多个前端管道传播的信息的同步的系统和方法。通常，这些多个前端管道响应于失速状态而变得异步，并且通过冲洗两个前端管道以及通过在不同的时间段内选择性地将这些前端管道从其失速状态中选择性地释放而重新建立同步。

10. 发明授权

US5742804A Instruction prefetch mechanism utilizing a branch predict instruction 失效
标题翻译：使用分支预测指令的指令预取机制
公开(公告)号：US5742804A
公开(公告)日：1998-04-21
申请号：US685607
申请日：1996-07-24
申请人： Tse-Yu Yeh , Mircea Poplingher , Kent G. Fielden , Hans Mulder , Rajiv Gupta , Dale Morris , Michael Schlansker
发明人： Tse-Yu Yeh , Mircea Poplingher , Kent G. Fielden , Hans Mulder , Rajiv Gupta , Dale Morris , Michael Schlansker
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/3846
摘要： A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.
摘要翻译：在程序指令序列的执行中减少指令提取损失的处理器和方法包括在分支之前的位置处插入到程序中的分支预测指令。分支预测指令具有指定可能被采用或未被采用的分支的操作码，并且还指定分支的目标地址。从目标地址开始的目标指令块被预取到处理器的指令高速缓存中，使得指令在程序中遇到分支的点之前可用于执行。操作码还指定了目标指令块的大小的指示，以及由分支预测指令导致目标的程序序列中的路径的跟踪向量，以更好地利用有限的存储器带宽。

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