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1. 发明申请

US20060256621A1 Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器和用于将数据写入非易失性半导体存储器的方法
公开(公告)号：US20060256621A1
公开(公告)日：2006-11-16
申请号：US11127022
申请日：2005-05-11
申请人： Luca de Ambroggi , Francesco Brani
发明人： Luca de Ambroggi , Francesco Brani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491
摘要： Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit (B1) and the second bit (B2) coincide with their respective initial states and includes maintaining the initial states of the first bit (B1) and the second bit (B2). A second step is executed if both the first bit (B1) and the second bit (B2) have erased final states and the initial states of both the first bit (B1) and the second bit (B2) were not erased and includes erasing both the first bit (B1) and the second bit (B2). A third step is executed if neither the first bit (B1) nor the second bit (B2) is to be changed from a programmed initial state to an erased final state and includes programming the first bit (B1) if the first bit (B1) is to be changed from an erased initial state to a programmed final state, and/or programming the second bit (B2) if the second bit (B2) is to be changed from an erased initial state to a programmed final state. A fourth step is executed if only one of the first bit (B1) and the second bit (B2) is to be changed from a programmed initial state to an erased final state and includes first erasing both the first bit (B1) and the second bit (B2) and then programming the first bit (B1) if the first bit (B1) is programmed in the final state or programming the second bit (B2) if the second bit (B2) is programmed in the final state.
摘要翻译：使用至少四个步骤之一将数据写入非易失性半导体存储器。如果第一比特（B 1）和第二比特（B 2）的最终状态与它们各自的初始状态一致，则执行第一步骤，并且包括维持第一比特（B 1）的初始状态和第二比特（B 2）。如果第一位（B 1）和第二位（B 2）都已经擦除最终状态并且第一位（B 1）和第二位（B 2）的初始状态都没有被擦除，则执行第二步并且包括擦除第一位（B 1）和第二位（B 2）。如果第一位（B 1）和第二位（B 2）都不能从编程的初始状态改变为擦除的最终状态，则执行第三步，并且如果第一位（B 1）和第二位（B 1）将从擦除的初始状态改变为编程的最终状态，和/或如果将第二位（B 2）从擦除的初始状态改变为编程的，则对第二位（B 2）进行编程最终状态。如果仅将第一位（B 1）和第二位（B 2）中的一个从编程的初始状态改变为擦除的最终状态，则执行第四步，并且包括首先擦除第一位（B 1）和第二位（B 2），然后如果第一位（B 1）被编程在最终状态，则编程第一位（B 1），或者如果第二位（B 2）是编程在最终状态。

2. 发明申请

US20080082762A1 Memory systems and methods of operating the memory systems 有权
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080082762A1
公开(公告)日：2008-04-03
申请号：US11529711
申请日：2006-09-28
申请人： Andreas Taeuber , Detlev Richter , Luca de Ambroggi , Rainer Spielberg
发明人： Andreas Taeuber , Detlev Richter , Luca de Ambroggi , Rainer Spielberg
IPC分类号： G06F13/00
CPC分类号： G06F13/4239
摘要： In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.
摘要翻译：在本发明的一个实施例中，提供了一种操作存储器系统的方法，包括同时从存储器系统的多个存储器读取数据，并以存储器系统的I / O端口的输出通道容量从存储器系统输出数据所述存储器系统通过将从所述多个存储器中的至少一些存储器读取的数据的数据总线宽度转换为所述I / O端口的数据总线宽度。

3. 发明申请

US20080080226A1 Memory system and method of operating the memory system 审中-公开
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080080226A1
公开(公告)日：2008-04-03
申请号：US11526850
申请日：2006-09-25
申请人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
发明人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/5614 , G11C7/1006 , G11C7/22 , G11C11/16 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2207/107 , G11C2211/5641
摘要： A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.
摘要翻译：存储器系统包括多个电阻存储单元区域，至少包括第一电阻存储单元区域和第二电阻存储单元区域，第一电阻存储单元区域形成有多个电阻存储单元，以第一数据存储速度存储数据形成有以低于第一数据存储速度的第二数据存储速度存储数据的多个电阻性存储单元形成的第二电阻性存储单元区域，以及控制器，用于控制多个电阻性存储单元区域之间的数据传输。

4. 发明授权

US07295477B2 Semiconductor memory device and method for writing data into the semiconductor memory device 有权
标题翻译：半导体存储器件和用于将数据写入半导体存储器件的方法
公开(公告)号：US07295477B2
公开(公告)日：2007-11-13
申请号：US11229003
申请日：2005-09-16
申请人： Luca de Ambroggi , Thomas Kern
发明人： Luca de Ambroggi , Thomas Kern
IPC分类号： G11C7/10
CPC分类号： G11C16/0475 , G11C16/0491 , G11C16/12 , G11C16/24
摘要： A semiconductor memory device comprises a wordline (40), a first bitline (21a), two second bitlines (22a, 22b), a first memory cell (100a) and a second memory cell (100b). The first memory cell (100a) is coupled to the wordline (40), one of the second bitlines (22a) and the first bitline (21a). The second memory cell (100b) is coupled to the wordline (40), the other second bitline (22b) and the first bitline (21a). Each memory cell (100a, 100b) stores a first bit (101) and a second bit (102). The semiconductor device further comprises a programming unit (2) coupled to the wordline (40) and the first and the second bitlines (21a, 22a, 22b). The programming unit (2) enables to apply a first programming potential (V1) to the wordline (40) and to apply a third programming potential (V3) to the second bitlines (22a, 22b) while applying a second programming potential (V2) to the first bitline (21a) in order to program the first bit (101) of the second memory cell (100b) and the second bit (102) of the first memory cell (100a).
摘要翻译：半导体存储器件包括字线（40），第一位线（21a），两个第二位线（22a，22b），第一存储器单元（100A）和第二存储器单元（100b）。第一存储单元（100a）耦合到字线（40），第二位线（22A）和第一位线（21a）之一。第二存储单元（100b）耦合到字线（40），另一第二位线（22b）和第一位线（21a）。每个存储单元（100a，100b）存储第一位（101）和第二位（102）。半导体器件还包括耦合到字线（40）和第一和第二位线（21a，22a，22b）的编程单元（2）。编程单元（2）使得能够将第一编程电位（V1）施加到字线（40）并且将第三编程电位（V 3）施加到第二位线（22a，22b），同时施加第二编程为了对第一存储单元（100b）的第一位（101）和第一存储单元（100a）的第二位（102）进行编程，电位（V 2）到第一位线（21a）。

5. 发明授权

US07187589B2 Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器和用于将数据写入非易失性半导体存储器的方法
公开(公告)号：US07187589B2
公开(公告)日：2007-03-06
申请号：US11127022
申请日：2005-05-11
申请人： Luca de Ambroggi , Francesco Maria Brani
发明人： Luca de Ambroggi , Francesco Maria Brani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491
摘要： Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit (B1) and the second bit (B2) coincide with their respective initial states and includes maintaining the initial states of the first bit (B1) and the second bit (B2). A second step is executed if both the first bit (B1) and the second bit (B2) have erased final states and the initial states of both the first bit (B1) and the second bit (B2) were not erased and includes erasing both the first bit (B1) and the second bit (B2). A third step is executed if neither the first bit (B1) nor the second bit (B2) is to be changed from a programmed initial state to an erased final state and includes programming the first bit (B1) if the first bit (B1) is to be changed from an erased initial state to a programmed final state, and/or programming the second bit (B2) if the second bit (B2) is to be changed from an erased initial state to a programmed final state. A fourth step is executed if only one of the first bit (B1) and the second bit (B2) is to be changed from a programmed initial state to an erased final state and includes first erasing both the first bit (B1) and the second bit (B2) and then programming the first bit (B1) if the first bit (B1) is programmed in the final state or programming the second bit (B2) if the second bit (B2) is programmed in the final state.
摘要翻译：使用至少四个步骤之一将数据写入非易失性半导体存储器。如果第一比特（B 1）和第二比特（B 2）的最终状态与它们各自的初始状态一致，则执行第一步骤，并且包括维持第一比特（B 1）的初始状态和第二比特（B 2）。如果第一位（B 1）和第二位（B 2）都已经擦除最终状态并且第一位（B 1）和第二位（B 2）的初始状态都没有被擦除，则执行第二步并且包括擦除第一位（B 1）和第二位（B 2）。如果第一位（B 1）和第二位（B 2）都不能从编程的初始状态改变为擦除的最终状态，则执行第三步，并且如果第一位（B 1）和第二位（B 1）将从擦除的初始状态改变为编程的最终状态，和/或如果将第二位（B 2）从擦除的初始状态改变为编程的，则对第二位（B 2）进行编程最终状态。如果仅将第一位（B 1）和第二位（B 2）中的一个从编程的初始状态改变为擦除的最终状态，则执行第四步，并且包括首先擦除第一位（B 1）和第二位（B 2），然后如果第一位（B 1）被编程在最终状态，则编程第一位（B 1），或者如果第二位（B 2）是编程在最终状态。

6. 发明授权

US07783826B2 Data bus width converter 有权
标题翻译：数据总线宽度转换器
公开(公告)号：US07783826B2
公开(公告)日：2010-08-24
申请号：US11529711
申请日：2006-09-28
申请人： Andreas Taeuber , Detlev Richter , Luca de Ambroggi , Rainer Spielberg
发明人： Andreas Taeuber , Detlev Richter , Luca de Ambroggi , Rainer Spielberg
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F13/4239
摘要： In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.
摘要翻译：在本发明的一个实施例中，提供了一种操作存储器系统的方法，包括同时从存储器系统的多个存储器读取数据，并以存储器系统的I / O端口的输出通道容量从存储器系统输出数据所述存储器系统通过将从所述多个存储器中的至少一些存储器读取的数据的数据总线宽度转换为所述I / O端口的数据总线宽度。

7. 发明申请

US20080082776A1 Memories, method of storing data in a memory and method of determining memory cell sector quality 有权
标题翻译：存储器，将数据存储在存储器中的方法和确定存储器单元扇区质量的方法
公开(公告)号：US20080082776A1
公开(公告)日：2008-04-03
申请号：US11541392
申请日：2006-09-29
申请人： Rainer Spielberg , Detlev Richter , Andreas Taeuber , Luca de Ambroggi
发明人： Rainer Spielberg , Detlev Richter , Andreas Taeuber , Luca de Ambroggi
IPC分类号： G06F12/00
CPC分类号： G11C29/50 , G11C11/5628 , G11C11/5678 , G11C13/0002 , G11C13/0069 , G11C2029/4402 , G11C2029/5002 , G11C2211/5641
摘要： A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.
摘要翻译：提供了一种将数据存储在存储器中的方法，包括测试多个存储单元扇区中的多个存储单元。每个存储单元扇区包括多个存储单元。根据各存储单元扇区的存储单元的测试结果，每个存储单元扇区被分类为多个质量等级的至少一个质量等级。根据各个存储单元扇区的质量等级，将数据存储在分类的存储单元扇区的存储单元中。

8. 发明授权

US07190621B2 Sensing scheme for a non-volatile semiconductor memory cell 有权
标题翻译：用于非易失性半导体存储器单元的感测方案
公开(公告)号：US07190621B2
公开(公告)日：2007-03-13
申请号：US11145551
申请日：2005-06-03
申请人： Marco Redaelli , Luca de Ambroggi
发明人： Marco Redaelli , Luca de Ambroggi
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/3436 , G11C11/5642 , G11C16/0466 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5634 , G11C2211/5645
摘要： A method of sensing a state of a non-volatile semiconductor memory cell is provided. A memory cell current as well as a comparative current generated from at least one reference cell are compared with a predefined reference current while the gate voltages of the cells are varied. Sense amplifiers detect which of said currents first reaches the predefined reference current. The order of reaching the reference current is indicative of the state of the memory cell. In a preferred embodiment of the invention the comparative current is generated as an average of an erased reference cell current and a programmed reference cell current.
摘要翻译：提供了一种感测非易失性半导体存储单元的状态的方法。将存储单元电流以及从至少一个参考单元产生的比较电流与预定参考电流进行比较，同时单元的栅极电压变化。感测放大器检测哪个电流首先达到预定义的参考电流。达到参考电流的顺序表示存储单元的状态。在本发明的优选实施例中，比较电流被产生为擦除的参考单元电流和编程的参考单元电流的平均值。

9. 发明授权

US07355468B2 Voltage generator circuit, method for providing an output voltage and electronic memory device 有权
标题翻译：电压发生器电路，提供输出电压的方法和电子存储器件
公开(公告)号：US07355468B2
公开(公告)日：2008-04-08
申请号：US11473519
申请日：2006-06-23
申请人： Luca de Ambroggi , Giacomo Curatolo
发明人： Luca de Ambroggi , Giacomo Curatolo
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C16/30
摘要： A voltage generator circuit provides an output voltage that is higher than an input voltage. The voltage generator circuit includes an input terminal receiving the input voltage, and an output terminal providing the output voltage. A pre-charge element is coupled between the input terminal and the output terminal, and a capacitance circuit is coupled to the input terminal and to the output terminal.
摘要翻译：电压发生器电路提供高于输入电压的输出电压。电压发生器电路包括接收输入电压的输入端子和提供输出电压的输出端子。预充电元件耦合在输入端子和输出端子之间，并且电容电路耦合到输入端子和输出端子。

10. 发明申请

US20070296486A1 VOLTAGE GENERATOR CIRCUIT, METHOD FOR PROVIDING AN OUTPUT VOLTAGE AND ELECTRONIC MEMORY DEVICE 有权
标题翻译：电压发生器电路，输出电压和电子存储器件的提供方法
公开(公告)号：US20070296486A1
公开(公告)日：2007-12-27
申请号：US11473519
申请日：2006-06-23
申请人： Luca de Ambroggi , Giacomo Curatolo
发明人： Luca de Ambroggi , Giacomo Curatolo
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C16/30
摘要： A voltage generator circuit provides an output voltage that is higher than an input voltage. The voltage generator circuit includes an input terminal receiving the input voltage, and an output terminal providing the output voltage. A pre-charge element is coupled between the input terminal and the output terminal, and a capacitance circuit is coupled to the input terminal and to the output terminal.
摘要翻译：电压发生器电路提供高于输入电压的输出电压。电压发生器电路包括接收输入电压的输入端子和提供输出电压的输出端子。预充电元件耦合在输入端子和输出端子之间，并且电容电路耦合到输入端子和输出端子。

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