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1. 发明授权

US07295477B2 Semiconductor memory device and method for writing data into the semiconductor memory device 有权
标题翻译：半导体存储器件和用于将数据写入半导体存储器件的方法
公开(公告)号：US07295477B2
公开(公告)日：2007-11-13
申请号：US11229003
申请日：2005-09-16
申请人： Luca de Ambroggi , Thomas Kern
发明人： Luca de Ambroggi , Thomas Kern
IPC分类号： G11C7/10
CPC分类号： G11C16/0475 , G11C16/0491 , G11C16/12 , G11C16/24
摘要： A semiconductor memory device comprises a wordline (40), a first bitline (21a), two second bitlines (22a, 22b), a first memory cell (100a) and a second memory cell (100b). The first memory cell (100a) is coupled to the wordline (40), one of the second bitlines (22a) and the first bitline (21a). The second memory cell (100b) is coupled to the wordline (40), the other second bitline (22b) and the first bitline (21a). Each memory cell (100a, 100b) stores a first bit (101) and a second bit (102). The semiconductor device further comprises a programming unit (2) coupled to the wordline (40) and the first and the second bitlines (21a, 22a, 22b). The programming unit (2) enables to apply a first programming potential (V1) to the wordline (40) and to apply a third programming potential (V3) to the second bitlines (22a, 22b) while applying a second programming potential (V2) to the first bitline (21a) in order to program the first bit (101) of the second memory cell (100b) and the second bit (102) of the first memory cell (100a).
摘要翻译：半导体存储器件包括字线（40），第一位线（21a），两个第二位线（22a，22b），第一存储器单元（100A）和第二存储器单元（100b）。第一存储单元（100a）耦合到字线（40），第二位线（22A）和第一位线（21a）之一。第二存储单元（100b）耦合到字线（40），另一第二位线（22b）和第一位线（21a）。每个存储单元（100a，100b）存储第一位（101）和第二位（102）。半导体器件还包括耦合到字线（40）和第一和第二位线（21a，22a，22b）的编程单元（2）。编程单元（2）使得能够将第一编程电位（V1）施加到字线（40）并且将第三编程电位（V 3）施加到第二位线（22a，22b），同时施加第二编程为了对第一存储单元（100b）的第一位（101）和第一存储单元（100a）的第二位（102）进行编程，电位（V 2）到第一位线（21a）。

2. 发明授权

US09389999B2 System and method for emulating an EEPROM in a non-volatile memory device 有权
标题翻译：用于在非易失性存储器件中仿真EEPROM的系统和方法
公开(公告)号：US09389999B2
公开(公告)日：2016-07-12
申请号：US13587993
申请日：2012-08-17
申请人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Edvin Paparisto , Thomas Nirschl
发明人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Edvin Paparisto , Thomas Nirschl
IPC分类号： G06F12/00 , G06F12/02 , G11C16/10
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G11C16/105
摘要： The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.
摘要翻译：本发明涉及一种电子存储器系统，更具体地说，涉及用于在非易失性存储器件中仿真电可擦除可编程只读存储器的系统，以及一种以非易失性存储器模拟电可擦除可编程只读存储器的方法存储设备。根据实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，该系统包括闪存，其中闪存可配置成第一区域和第二区域，其中第一区域适于存储第一类数据和第二区域适于存储第二种不同类别的数据。

3. 发明授权

US09251864B2 System and method for providing voltage supply protection in a memory device 有权
标题翻译：在存储器件中提供电压保护的系统和方法
公开(公告)号：US09251864B2
公开(公告)日：2016-02-02
申请号：US13605129
申请日：2012-09-06
申请人： Jan Otterstedt , Wolf Allers , Mihail Jefremow , Edvin Paparisto , Leonardo Castro , Thomas Kern
发明人： Jan Otterstedt , Wolf Allers , Mihail Jefremow , Edvin Paparisto , Leonardo Castro , Thomas Kern
IPC分类号： G11C29/04 , G11C29/02 , G11C5/14
CPC分类号： G11C29/83 , G11C5/143 , G11C29/02 , G11C29/04 , G11C29/832
摘要： The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.
摘要翻译：本发明涉及一种电子存储器系统，更具体地说，涉及一种用于在存储器件中提供电压保护的系统，以及一种在存储器件中提供电压保护的方法。根据实施例，提供了一种用于在存储器件中提供电压保护的系统，该系统包括一个存储器阵列，该存储器阵列包括布置在多组存储器单元中的多个存储单元，以及多个限流元件，其中每组存储器单元与至少一个限流元件相关联。

4. 发明授权

US09070466B2 Mismatch error reduction method and system for STT MRAM 有权
标题翻译： STT MRAM的不匹配误差减少方法和系统
公开(公告)号：US09070466B2
公开(公告)日：2015-06-30
申请号：US13605693
申请日：2012-09-06
申请人： Mihail Jefremow , Wolf Allers , Jan Otterstedt , Christian Peters , Thomas Kern
发明人： Mihail Jefremow , Wolf Allers , Jan Otterstedt , Christian Peters , Thomas Kern
IPC分类号： G11C11/16
CPC分类号： G11C11/1673
摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
摘要翻译：本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。根据本发明的一个方面，一种用于读取存储单元的方法包括将来自存储单元的单元电流与来自参考源的参考电流组合以产生平均电流，使平均电流能够流过第一镜像晶体管在参考路径中的感测路径和第二镜像晶体管中，将电流失配存储在耦合到第一镜面晶体管和第二镜像晶体管的栅极的电容器上，将存储器单元与参考路径断开并将参考源与感测路径，使得电池电流仅能够流过感测路径，并且确定存储器单元的输出电平。

5. 发明申请

US20130305119A1 Method and Device for Correction of Ternary Stored Binary Data 有权
标题翻译：用于校正三元存储二进制数据的方法和装置
公开(公告)号：US20130305119A1
公开(公告)日：2013-11-14
申请号：US13466400
申请日：2012-05-08
申请人： Thomas Kern , Michael Goessei
发明人： Thomas Kern , Michael Goessei
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/13 , G06F11/1012 , G11C2029/0411
摘要： The invention relates to a device and a method for storing binary data in a storage device, in which the binary data is transformed to and stored as ternary data. The storage device uses memory cells capable of storing three states. The device and method furthermore are configured to identify and correct falsified ternary data when reading and outputting the data from storage device.
摘要翻译：本发明涉及将二进制数据存储在存储装置中的装置和方法，其中二进制数据被转换并存储为三进制数据。存储装置使用能够存储三种状态的存储单元。该装置和方法还被配置为当从存储装置读取和输出数据时，识别和纠正伪造的三进制数据。

6. 发明授权

US08539321B2 Apparatus and method for correcting at least one bit error within a coded bit sequence 有权
标题翻译：用于校正编码比特序列内的至少一个比特差错的装置和方法
公开(公告)号：US08539321B2
公开(公告)日：2013-09-17
申请号：US12943520
申请日：2010-11-10
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stéphane Lacouture
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stéphane Lacouture
IPC分类号： H04M13/00
CPC分类号： H03M13/151 , H03M13/152 , H03M13/155 , H03M13/1575 , H03M13/159 , H03M13/616 , H03M13/6575
摘要： An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
摘要翻译：用于校正编码比特序列中的至少一个比特误差的装置包括误差校正子发生器和比特误差校正器。错误校正子发生器确定通过校验矩阵与编码比特序列的乘法导出的编码比特序列的错误校正。

7. 发明申请

US20120144260A1 Apparatus and Method for Detecting an Error Within a Coded Binary Word 有权
标题翻译：用于检测编码二进制字中的错误的装置和方法
公开(公告)号：US20120144260A1
公开(公告)日：2012-06-07
申请号：US12959838
申请日：2010-12-03
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： G06F11/10
CPC分类号： H03M13/3776 , H03M13/13 , H03M13/19 , H03M13/3738
摘要： An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.
摘要翻译：用于检测编码二进制字中的误差的装置包括误差校正器和误差检测器。误差校正器校正由错误校正码编码的故障编码二进制字的位的有故障子集内的可校正位错误，使得校正的位子集等于纠错码字的相应子集代码，如果错误校正器工作无效。此外，误差检测器确定指示误差检测器输入二进制字是否是纠错码的码字的错误检测比特序列。误差检测器输入二进制字基于包含校正的比特子集的校正的编码二进制字，并且最大限度地存在故障编码的二进制字的位的适当子集。

8. 发明申请

US20090059672A1 SELF-TIMED INTEGRATING DIFFERENTIAL CURRENT SENSE AMPLIFIER 有权
标题翻译：自适应积分差分电流检测放大器
公开(公告)号：US20090059672A1
公开(公告)日：2009-03-05
申请号：US11845534
申请日：2007-08-27
申请人： Thomas Kern
发明人： Thomas Kern
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： G11C7/062 , G11C7/14 , G11C16/28 , G11C2207/063
摘要： A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. Integration continues until a desired voltage or time is reached, resulting in a sufficiently reliable output. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.
摘要翻译：参考电流积分器和感测电流积分器被耦合以形成差分读出放大器。差分读出放大器被耦合以从闪速存储器接收位线电流信号，并且参考电流积分器被耦合以从参考存储器单元接收电流信号。整合继续，直到达到所需的电压或时间，从而产生足够可靠的输出。差分电流积分放大器也用于仪表，通信，数据存储，感应，生物医学设备和模数转换。

9. 发明申请

US20070288111A1 Systems and methods for calculating alerts based on pegging 有权
标题翻译：基于挂钩计算警报的系统和方法
公开(公告)号：US20070288111A1
公开(公告)日：2007-12-13
申请号：US11448303
申请日：2006-06-07
申请人： Thomas Kern
发明人： Thomas Kern
IPC分类号： G06F19/00
CPC分类号： G06Q10/06
摘要： A system and method for performing supply chain planning, includes providing a plurality of demand orders, each demand order including at least one input interface node, each input interface node identifying a type of material required by said demand order, a quantity of the material required by said demand order and a requirements date the material is required by said demand order, providing a plurality of supply orders, each supply order including at least one output interface node, each output interface node identifying a type of material provided by said supply order, a quantity of the material provided by said supply order and a date the material is provided by said supply order, combining a plurality of said demand orders into an aggregated demand order and forming an aggregated demand time line, each aggregated demand order indicating a quantity of material required, the quantity of material required being a sum of the quantities of the material required by said plurality of demand orders combined into the aggregated demand order and performing an operation for pegging the plurality of supply orders to the aggregated demand orders
摘要翻译：一种用于执行供应链规划的系统和方法，包括提供多个需求订单，每个需求订单包括至少一个输入接口节点，每个输入接口节点标识所述需求订单所需的材料类型，所需材料的数量通过所述需求订单和要求日期，所述需求订单需要材料，提供多个供应订单，每个供应订单包括至少一个输出接口节点，每个输出接口节点标识由所述供应订单提供的材料的类型，由所述供应单提供的材料的数量以及所述供应订单提供的材料的日期，将多个所述需求订单组合成聚合的需求订单并形成汇总的需求时间线，每个汇总的需求订单指示数量所需的材料，所需材料的数量是所述多个材料所需的材料的数量的总和并将订单组合成聚合需求订单，并执行将多个供应订单与聚集的需求订单挂钩的操作

10. 发明申请

US20060184898A1 Context menu dependency on many objects of different type 有权
标题翻译：上下文菜单依赖于不同类型的许多对象
公开(公告)号：US20060184898A1
公开(公告)日：2006-08-17
申请号：US11351397
申请日：2006-02-10
申请人： Thomas Kern
发明人： Thomas Kern
IPC分类号： G06F9/00
CPC分类号： G06F17/30126 , G06F3/048 , G06F3/0481 , G06F3/04817 , G06F3/0482 , G06F3/0483 , G06F3/0484 , G06F3/04842 , Y10S715/975
摘要： A computer implemented method is represented for providing to a user a context menu with entries representing relationships. The relationships are applicable to relate objects selected from a set of objects. The method comprises following method operations: receiving a first identification of a first selected object from the set of objects, receiving a second identification of a second selected object from the set of objects, identifying object types of the selected objects in a plurality of object types, determining one or more relationship types of which one or more relationships are applicable to the selected objects by using the identified object types, and generating for the context menu an entry representing a relationship of the one or more relationship types, wherein the relationship is selectable by the user to be created between the selected objects.
摘要翻译：代表用于向用户提供具有表示关系的条目的上下文菜单的计算机实现的方法。这些关系适用于从一组对象中选择的对象。该方法包括以下方法操作：从所述对象集合接收第一所选对象的第一标识，从所述对象集合中接收第二所选对象的第二标识，识别多个对象类型中的所选对象的对象类型通过使用所识别的对象类型来确定一个或多个关系适用于所选择的对象的一个或多个关系类型，以及为所述上下文菜单生成表示所述一个或多个关系类型的关系的条目，其中所述关系是可选择的由用户在所选对象之间创建。

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