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1. 发明授权

US07348870B2 Structure and method of fabricating a hinge type MEMS switch 有权
标题翻译：制造铰链式MEMS开关的结构和方法
公开(公告)号：US07348870B2
公开(公告)日：2008-03-25
申请号：US10905449
申请日：2005-01-05
申请人： Louis C. Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis C. Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.
摘要翻译：描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松动地连接到引导柱; 上下电极对; 以及由可动导电板连接和断开的上下互连布线。当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

2. 发明授权

US07657995B2 Method of fabricating a microelectromechanical system (MEMS) switch 失效
标题翻译：制造微机电系统（MEMS）开关的方法
公开(公告)号：US07657995B2
公开(公告)日：2010-02-09
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01H65/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要翻译：一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

3. 发明申请

US20080318415A1 INTERCONNECT STRUCTURES WITH ENCASING CAP AND METHODS OF MAKING THEREOF 有权
标题翻译：具有加密帽的互连结构及其制造方法
公开(公告)号：US20080318415A1
公开(公告)日：2008-12-25
申请号：US12199407
申请日：2008-08-27
申请人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，包括：在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

4. 发明授权

US08304912B2 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US08304912B2
公开(公告)日：2012-11-06
申请号：US12054644
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

5. 发明申请

US20080164525A1 Structure and Method for Mosfet Gate Electrode Landing Pad 有权
标题翻译： Mosfet栅极电极着陆垫的结构和方法
公开(公告)号：US20080164525A1
公开(公告)日：2008-07-10
申请号：US12054644
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

6. 发明授权

US07488677B2 Interconnect structures with encasing cap and methods of making thereof 失效
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US07488677B2
公开(公告)日：2009-02-10
申请号：US11503259
申请日：2006-08-14
申请人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carol Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carol Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，包括在电介质材料中提供互连结构，使电介质材料凹陷，使得互连结构的一部分在电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

7. 发明授权

US06661097B1 Ti liner for copper interconnect with low-k dielectric 失效
标题翻译：用于低k电介质的铜互连的Ti衬垫
公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译：在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

8. 发明授权

US07041552B2 Integrated metal-insulator-metal capacitor and metal gate transistor 失效
标题翻译：集成金属 - 绝缘体 - 金属电容器和金属栅极晶体管
公开(公告)号：US07041552B2
公开(公告)日：2006-05-09
申请号：US10787487
申请日：2004-02-26
申请人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Kwong Hon Wong
IPC分类号： H01L21/8242
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/28114 , H01L27/0629 , H01L27/10805 , H01L27/1085 , H01L27/10885 , H01L29/42376 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66545
摘要： An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprise a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure.
摘要翻译：公开了一种集成电路结构，其包括一对电容器，每个电容器具有由绝缘体分隔的金属板和与电容器电连接的金属栅极半导体晶体管。晶体管的金属栅极和每个电容器的金属板之一在集成电路结构中包括相同的金属电平。更具体地，每个电容器包括垂直电容器，其具有垂直于下金属板上的上金属板，并且晶体管的每个金属栅极和电容器的每个上金属板在集成电路结构中包括相同的金属电平。

9. 发明授权

US6022801A Method for forming an atomically flat interface for a highly disordered metal-silicon barrier film 失效
标题翻译：用于形成高度无序的金属 - 硅阻挡膜的原子平坦界面的方法
公开(公告)号：US6022801A
公开(公告)日：2000-02-08
申请号：US25718
申请日：1998-02-18
申请人： Anthony G. Domenicucci , Lynne M. Gignac , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
发明人： Anthony G. Domenicucci , Lynne M. Gignac , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L21/283
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76856 , H01L21/28568 , H01L21/3212 , H01L2221/1078
摘要： A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.
摘要翻译：公开了一种形成具有原子平坦界面的导电接触的方法。含有钴和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。导电材料沉积在退火形成的结构的顶部。形成了防止导电材料扩散到下面的硅衬底中的平坦界面。该方法可以用于形成非常小的器件和浅结的接触，例如ULSI浅结所需要的。

10. 发明授权

US07491660B2 Method of forming nitride films with high compressive stress for improved PFET device performance 失效
标题翻译：形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法
公开(公告)号：US07491660B2
公开(公告)日：2009-02-17
申请号：US11873721
申请日：2007-10-17
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469 , C23C16/00 , C23C14/10 , C23C14/00
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译：提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。这种压应力允许改进PFET中的器件性能。使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。氮化物层的厚度在约300-2000埃的范围内。

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