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1. 发明授权

US5819072A Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints 失效
标题翻译：使用四态模拟器测试具有可变时序约束的集成电路设计的方法
公开(公告)号：US5819072A
公开(公告)日：1998-10-06
申请号：US671432
申请日：1996-06-27
申请人： Louis B. Bushard , Peter B. Criswell , Douglas A. Fuller , James E. Rezek , Richard F. Paul
发明人： Louis B. Bushard , Peter B. Criswell , Douglas A. Fuller , James E. Rezek , Richard F. Paul
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031
摘要： Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.
摘要翻译：对于对于多个并行路径具有不同时序约束的电路设计执行关键路径时序分析的方法。方法包括清除电路设计的状态，将电路设计中的控制线设置为所选择的一组控制信号，以及通过使用所选择的一组控制来模拟电路设计来识别要标记的时序分析的电路设计的阻塞网信号作为输入信号。识别的阻塞点被添加到标识要分析的电路设计中的路径的列表。处理所有可能的控制信号组。然后使用列表作为输入数据对电路设计进行时序分析。关键的一步是识别阻塞点。针对具有未知值的电路设计中的栅极的每个净输入识别阻塞点，以及针对所选择的一组控制信号的来自栅极的输出网上的已知值。输入到定时分析工具的阻塞点确保在关键路径时序分析期间对这些网络进行分析，因此检测到电路设计中的所有可能的定时违规。

2. 发明授权

US07356647B1 Cache with integrated capability to write out entire cache 有权
标题翻译：具有集成功能的缓存来写出整个缓存
公开(公告)号：US07356647B1
公开(公告)日：2008-04-08
申请号：US11209227
申请日：2005-08-23
申请人： Robert H. Andrighetti , Donald C. Englin , Douglas A. Fuller
发明人： Robert H. Andrighetti , Donald C. Englin , Douglas A. Fuller
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0817
摘要： A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of first and second values. The controller selectively writes all of the modified information in the cache memory to the system memory responsive to the command. Also in response to this command, all of the information is invalidated in the cache memory if the mode register is set to the second value. In one embodiment, none of the information except the modified data is invalidated if the mode register is set to the first value. The second value may be utilized to efficiently reassign one or more cache memories to a new partition.
摘要翻译：数据处理系统的缓存布置提供由维护处理器的命令发起的高速缓存刷新操作。高速缓存装置包括高速缓冲存储器，模式寄存器和控制器。模式寄存器可由维护处理器设置为第一和第二值之一。控制器响应于该命令选择性地将高速缓冲存储器中的所有修改的信息写入系统存储器。此外，响应于该命令，如果模式寄存器被设置为第二值，则所有信息在高速缓冲存储器中被无效。在一个实施例中，如果模式寄存器被设置为第一值，则除了修改的数据之外的信息都不会失效。可以利用第二值来有效地将一个或多个高速缓冲存储器重新分配到新的分区。

3. 发明授权

US07478025B1 System and method to support dynamic partitioning of units to a shared resource 有权
标题翻译：支持将单位动态划分到共享资源的系统和方法
公开(公告)号：US07478025B1
公开(公告)日：2009-01-13
申请号：US10418887
申请日：2003-04-18
申请人： Douglas A. Fuller , David P. Williams
发明人： Douglas A. Fuller , David P. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A system and method for performing dynamic partitioning operations within a data processing system is disclosed. According to one embodiment, the current invention provides a system that allows an unit to be added to an executing data processing partition. The partition may include a shared resource that is receiving requests from other units that are already included within the partition. The inventive system includes means for programmably enabling the unit to the shared resource. Once the unit is so enabled, the system synchronizes the request arbitration being performed by this unit with the arbitration activities occurring within other units requesting access to the shared resource. This synchronization process prevents two units from attempting to simultaneously access the shared resource.
摘要翻译：公开了一种用于在数据处理系统内执行动态分区操作的系统和方法。根据一个实施例，本发明提供一种允许将单元添加到执行数据处理分区的系统。分区可以包括正在从已经包括在分区内的其他单元接收请求的共享资源。本发明的系统包括用于可编程地使单元能够使共享资源的装置。一旦该单元被启用，系统将由该单元执行的请求仲裁与请求访问共享资源的其他单元内发生的仲裁活动同步。此同步过程可防止两个单元尝试同时访问共享资源。

4. 发明授权

US5719783A Method and apparatus for performing timing analysis on a circuit design 失效
标题翻译：用于对电路设计进行时序分析的方法和装置
公开(公告)号：US5719783A
公开(公告)日：1998-02-17
申请号：US597847
申请日：1996-02-07
申请人： Joseph P. Kerzman , Duane G. Kurth , Douglas A. Fuller
发明人： Joseph P. Kerzman , Duane G. Kurth , Douglas A. Fuller
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing violations reported by a Critical Path Analysis (CPA) algorithm, while maintaining a performance advantage over a Path Enumeration (PE) algorithm. This is accomplished by providing a number of "pseudo" clocks to selected latches within the circuit design database, thereby tricking the CPA algorithm into reporting more timing violations than would otherwise be reported.
摘要翻译：一种用于对电路设计进行时序分析的方法和装置。本发明基本上提供路径枚举算法和关键路径算法之间的混合。因此，本发明增加了关键路径分析（CPA）算法报告的定时违规的数量和程度，同时保持了比路径枚举（PE）算法的性能优势。这是通过向电路设计数据库内的选择的锁存器提供多个“伪”时钟来实现的，从而将CPA算法欺骗到报告比否则报告的更多的定时违反。

5. 发明授权

US07562263B1 System and method for detecting and recovering from errors in a control store of an electronic data processing system 有权
标题翻译：用于检测和从电子数据处理系统的控制存储器中的错误中恢复的系统和方法
公开(公告)号：US07562263B1
公开(公告)日：2009-07-14
申请号：US11226499
申请日：2005-09-14
申请人： Kenneth L. Engelbrecht , Douglas A. Fuller , David C. Johnson
发明人： Kenneth L. Engelbrecht , Douglas A. Fuller , David C. Johnson
IPC分类号： G01F11/00
CPC分类号： G06F11/10
摘要： A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are detected and recovered from without any required interaction with an operating system of the data processing system. Thus, errors in the control store memory can be handled seamlessly and efficiently, without requiring a maintenance technician, or in some cases, a specialized operating system routine, to help diagnose and fix the error.
摘要翻译：提供了一种用于检测和从电子数据处理系统的控制存储器中的错误中恢复的系统和方法。在某些情况下，控制存储存储器中的错误被检测和恢复，而不需要与数据处理系统的操作系统进行所需的交互。因此，无需维护技术人员，或在某些情况下，专门的操作系统例程，可以无缝和高效地处理控制存储器中的错误，以帮助诊断和修复错误。

6. 发明授权

US06751756B1 First level cache parity error inject 失效
标题翻译：第一级缓存奇偶校验错误注入
公开(公告)号：US06751756B1
公开(公告)日：2004-06-15
申请号：US09727610
申请日：2000-12-01
申请人： Thomas D. Hartnett , John Steven Kuslak , Douglas A. Fuller
发明人： Thomas D. Hartnett , John Steven Kuslak , Douglas A. Fuller
IPC分类号： G06F1100
CPC分类号： G06F11/1064 , G06F9/30145 , G06F9/3861 , G06F11/2215 , G06F12/0802 , G11C29/02
摘要： A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.
摘要翻译：一种用于当将指令从读缓冲器复制到第一级高速缓存时，将奇偶校验错误选择性地注入数据处理系统的指令的系统和方法。根据可编程指示器选择性地注入奇偶校验错误，每个可编程指示符与存储在读缓冲器中的一个或多个指令相关联。错误注入系统还包括可编程操作模式，从而在例如从读缓冲器到第一级高速缓存的每个副本期间进行错误注入，或者在仅选择的回写序列期间将发生错误注入。该系统允许对指令处理器中的错误检测和恢复逻辑进行全面测试，并且还允许对与从第二级高速缓存或存储设备执行数据重新获取相关联的逻辑的全面测试。

7. 发明授权

US5796972A Method and apparatus for performing microcode paging during instruction execution in an instruction processor 失效
标题翻译：在指令处理器中的指令执行期间执行微代码寻呼的方法和装置
公开(公告)号：US5796972A
公开(公告)日：1998-08-18
申请号：US783614
申请日：1997-01-14
申请人： David C. Johnson , Douglas A. Fuller , Kenneth L. Engelbrecht , Gregory A. Marlan , Ronald G. Arnold , Gerald G. Fagerness
发明人： David C. Johnson , Douglas A. Fuller , Kenneth L. Engelbrecht , Gregory A. Marlan , Ronald G. Arnold , Gerald G. Fagerness
IPC分类号： G06F9/24 , G06F9/26 , G06F9/318 , G06F9/445
CPC分类号： G06F9/328 , G06F8/66 , G06F9/24 , G06F9/268 , G06F9/30145
摘要： Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.
摘要翻译：在指令处理器中的指令执行期间执行微代码寻呼的方法和装置。在优选实施例中，提供了包括微码ROM和微代码RAM的指令处理器。微代码ROM存储用于计算机系统的微代码的当前版本，并且微代码RAM存储微代码补丁指令。在指令执行期间，本发明根据指令是否需要补丁微代码指令，在微代码ROM的输出和微代码RAM之间进行选择。如果期望的微代码补丁指令未被存储在微代码RAM中，则指令处理器被暂时中断，并且将期望的微代码补丁指令或一组微代码补丁指令写入或分页到微代码RAM中。

8. 发明申请

US20170308564A1 SYSTEMS AND METHODS FOR IMPLEMENTING A MULTI-HOST RECORD LOCK DEADLOCK FEEDBACK MECHANISM 审中-公开
公开(公告)号：US20170308564A1
公开(公告)日：2017-10-26
申请号：US15133270
申请日：2016-04-20
申请人： Matthew E. Trautman , Linda J. Brock , Douglas A. Fuller , Edward C. Fisher , Michael J. Rieschl
发明人： Matthew E. Trautman , Linda J. Brock , Douglas A. Fuller , Edward C. Fisher , Michael J. Rieschl
IPC分类号： G06F17/30
CPC分类号： G06F16/2336
摘要： A method includes retrieving, by a processor, a first entry from a global wait list as a current waiting lock. The method further includes decreasing, by the processor, a deadlock timer of the current waiting lock. The method further includes determining, by the processor, whether the deadlock timer equals zero. The method further includes appending, by the processor, the current waiting lock to an end of a deadlock victim selection list, if the deadlock timer equals zero. The method further includes selecting, by the processor, a victim from the deadlock victim selection list.

9. 发明授权

US5726903A Method and apparatus for resolving conflicts between cell substitution recommendations provided by a drive strength adjust tool 失效
标题翻译：用于解决由驱动强度调整工具提供的电池替换建议之间的冲突的方法和装置
公开(公告)号：US5726903A
公开(公告)日：1998-03-10
申请号：US597931
申请日：1996-02-07
申请人： Joseph P. Kerzman , Douglas A. Fuller
发明人： Joseph P. Kerzman , Douglas A. Fuller
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and apparatus for efficiently identifying and resolving conflicts between conflicting cell substitution recommendations. Unlike the prior art, the present invention provides a resolving means within a data processing system to identify and resolve conflicting cell substitution recommendations. The resolving means may categorize the cell substitutions in accordance with a number of predetermined cell substitution types, wherein each of the cell substitution type may be assign a predetermined priority value. Thereafter, the resolving means may identify conflicting cell substitution recommendations, and resolve the conflicts in accordance with the predetermined priority scheme.
摘要翻译：一种用于有效地识别和解决冲突的细胞替代建议之间的冲突的方法和装置。与现有技术不同，本发明提供了一种数据处理系统内的解析装置，用于识别和解决冲突的小区替换建议。分解装置可以根据预定的小区替换类型的数目对小区替换进行分类，其中每个小区替换类型可以分配预定的优先级值。此后，解析装置可以识别冲突的小区替换建议，并且根据预定优先级方案来解决冲突。

10. 发明申请

US20170364545A1 SYSTEMS AND METHODS FOR IMPLEMENTING A MULTI-HOST RECORD LOCK MECHANISM 有权
公开(公告)号：US20170364545A1
公开(公告)日：2017-12-21
申请号：US15187973
申请日：2016-06-21
申请人： MICHAEL C. Otto , Carl R. Crandall , Forest F. Crocker , Lnda J. Brock , Douglas A. Fuller , Michael J. Rieschl
发明人： MICHAEL C. Otto , Carl R. Crandall , Forest F. Crocker , Lnda J. Brock , Douglas A. Fuller , Michael J. Rieschl
IPC分类号： G06F17/30 , G06F9/455
摘要： A method includes determining, by a processor, whether a program check condition exists. The method further includes determining, by the processor, whether a lock descriptor of a lock in a file lock table satisfies an unlocking condition. The method further includes releasing, by the processor, the lock by setting the lock descriptor's host identifier as zero. The method further includes determining, by the processor, whether any lock in the file lock table satisfies a lock conflict condition. The method further includes determining, by the processor, whether the file lock table includes any lock descriptor that satisfies a locking condition. The method further includes creating, by the processor, a new lock using the lock descriptor that satisfies the locking condition.

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