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1. 发明授权

US06973541B1 System and method for initializing memory within a data processing system 有权
标题翻译：在数据处理系统中初始化存储器的系统和方法
公开(公告)号：US06973541B1
公开(公告)日：2005-12-06
申请号：US10255495
申请日：2002-09-26
申请人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Kelvin S. Vartti , Stephen Sutter , Chad M. Sonmore
发明人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Kelvin S. Vartti , Stephen Sutter , Chad M. Sonmore
IPC分类号： G06F9/30 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30047 , G06F12/08 , G06F12/0891
摘要： An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a “page zero” instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, the IP issues one or more page zero requests using a background interface of the IP. In one embodiment, each request results in the initialization of a page of memory. While page zero requests are issued over the background interface, the IP may continue issuing other read and write requests to memory over a primary interface of the IP.
摘要翻译：提供了一种用于在数据处理系统中初始化存储器的改进的系统和方法。根据本发明的一个方面，提供了可以由指令处理器执行以启动存储器初始化的“页零”指令。在执行指令时，IP使用IP的后台接口发出一个或多个页面零请求。在一个实施例中，每个请求导致一页存储器的初始化。当通过后台接口发出页面零请求时，IP可以通过IP的主接口继续向存储器发出其他读取和写入请求。

2. 发明授权

US06976128B1 Cache flush system and method 失效
标题翻译：缓存刷新系统和方法
公开(公告)号：US06976128B1
公开(公告)日：2005-12-13
申请号：US10255420
申请日：2002-09-26
申请人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Donald C. Englin
发明人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Donald C. Englin
IPC分类号： G06F9/30 , G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/127
摘要： A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel “page flush” and “cache line flush” instructions are provided to flush a page and a cache line of memory data, respectively, from a cache to a main memory. In one embodiment, these instructions are included within the hardware instruction set of an Instruction Processor (IP). According to another aspect of the invention, flush operations are initiated using a background interface that interconnects the IP with its associated cache memory. A primary interface that also interconnects the IP to the cache memory is used to simultaneously issue higher-priority requests so that processor throughput is increased.
摘要翻译：提供了一种系统和方法，用于选择性地将数据从高速缓存存储器刷新到主存储器，而与用于管理高速缓存数据的替换算法无关。根据本发明的一个方面，提供了新颖的“页面刷新”和“高速缓存行刷新”指令，用于将存储器数据的页面和高速缓存行分别从缓存刷新到主存储器。在一个实施例中，这些指令被包括在指令处理器（IP）的硬件指令集中。根据本发明的另一方面，使用将IP与其相关联的高速缓冲存储器互连的后台接口来启动刷新操作。也将IP与高速缓冲存储器互连的主界面用于同时发出较高优先级的请求，从而提高处理器吞吐量。

3. 发明授权

US07603672B1 Programmable request handling system and method 有权
标题翻译：可编程请求处理系统和方法
公开(公告)号：US07603672B1
公开(公告)日：2009-10-13
申请号：US10744992
申请日：2003-12-23
申请人： Robert H. Andrighetti
发明人： Robert H. Andrighetti
IPC分类号： G06F9/46 , G06F3/00 , G06F13/28
CPC分类号： G06F9/30047 , G06F9/3863 , G06F12/0811 , G06F12/0857 , G06F12/0862 , G06F13/1642 , G06F2212/6028
摘要： A system and method is disclosed for prioritizing requests received from multiple requesters for presentation to a shared resource. The system includes logic that implements multiple priority schemes. This logic may be programmably configured to associate each of the requesters with any of the priority schemes. The priority scheme that is associated with the requester controls how that requester submits requests to the shared resource. The requests that have been submitted by any of the requesters in this manner are then processed in a predetermined order. This order is established using an absolute priority assigned to each of the requesters. This order may further be determined by assigning one or more requesters a priority that is relative to another requester. The absolute and relative priority assignments are programmable.
摘要翻译：公开了一种系统和方法，用于优先化从多个请求者接收的请求以呈现给共享资源。该系统包括实现多个优先级方案的逻辑。该逻辑可以可编程地配置为将每个请求者与任何优先级方案相关联。与请求者相关联的优先级方案控制请求者如何向共享资源提交请求。然后以预定的顺序处理由任何请求者以这种方式提交的请求。使用分配给每个请求者的绝对优先级建立此顺序。可以通过将一个或多个请求者分配给相对于另一请求者的优先级来进一步确定该顺序。绝对和相对优先级分配是可编程的。

4. 发明授权

US06993630B1 Data pre-fetch system and method for a cache memory 失效
标题翻译：缓存存储器的数据预取系统和方法
公开(公告)号：US06993630B1
公开(公告)日：2006-01-31
申请号：US10255393
申请日：2002-09-26
申请人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Donald C. Englin , Kelvin S. Vartti
发明人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Donald C. Englin , Kelvin S. Vartti
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.
摘要翻译：公开了一种用于预取数据信号的系统和方法。根据本发明的一个方面，指令处理器（IP）产生访问高速缓存内的数据信号的请求。将预定的请求提供给预取控制逻辑，其确定数据信号是否在高速缓存内可用。如果不是，数据信号从数据处理系统中的另一个存储器检索，并被存储到高速缓存。根据一个方面，可以可编程地选择生成预取请求的速率以匹配将相关联的数据信号请求提供给高速缓存的速率。在另一个实施例中，预取控制逻辑接收信息以使用将预取控制逻辑耦合到IP的专用接口来生成预取请求。

5. 发明授权

US07356647B1 Cache with integrated capability to write out entire cache 有权
标题翻译：具有集成功能的缓存来写出整个缓存
公开(公告)号：US07356647B1
公开(公告)日：2008-04-08
申请号：US11209227
申请日：2005-08-23
申请人： Robert H. Andrighetti , Donald C. Englin , Douglas A. Fuller
发明人： Robert H. Andrighetti , Donald C. Englin , Douglas A. Fuller
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0817
摘要： A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of first and second values. The controller selectively writes all of the modified information in the cache memory to the system memory responsive to the command. Also in response to this command, all of the information is invalidated in the cache memory if the mode register is set to the second value. In one embodiment, none of the information except the modified data is invalidated if the mode register is set to the first value. The second value may be utilized to efficiently reassign one or more cache memories to a new partition.
摘要翻译：数据处理系统的缓存布置提供由维护处理器的命令发起的高速缓存刷新操作。高速缓存装置包括高速缓冲存储器，模式寄存器和控制器。模式寄存器可由维护处理器设置为第一和第二值之一。控制器响应于该命令选择性地将高速缓冲存储器中的所有修改的信息写入系统存储器。此外，响应于该命令，如果模式寄存器被设置为第二值，则所有信息在高速缓冲存储器中被无效。在一个实施例中，如果模式寄存器被设置为第一值，则除了修改的数据之外的信息都不会失效。可以利用第二值来有效地将一个或多个高速缓冲存储器重新分配到新的分区。

6. 发明授权

US5471487A Stack read/write counter through checking 失效
标题翻译：通过检查堆栈读/写计数器
公开(公告)号：US5471487A
公开(公告)日：1995-11-28
申请号：US233232
申请日：1994-04-26
申请人： Robert H. Andrighetti
发明人： Robert H. Andrighetti
IPC分类号： G06F11/00
CPC分类号： G06F11/0751
摘要： An apparatus for efficiently detecting an error on a memory stack write pointer or a memory stack read pointer by continuously monitoring the relative position between the two pointers. Using this technique, the present invention may detect certain classes of errors that cannot be detected by other error detection methods such as redundancy. The present invention eliminates the need to provide full redundancy thereby potentially saving considerable cost, size and power in a typical computer system.
摘要翻译：一种用于通过连续地监视两个指针之间的相对位置来有效地检测存储器堆栈写入指针或存储器堆栈读取指针上的错误的装置。使用这种技术，本发明可以检测由诸如冗余的其他错误检测方法无法检测到的某些类别的错误。本发明消除了提供完全冗余的需要，从而在典型的计算机系统中潜在地节约了大量的成本，尺寸和功率。

7. 发明授权

US06934810B1 Delayed leaky write system and method for a cache memory 有权
标题翻译：延迟泄漏的写入系统和缓存的方法
公开(公告)号：US06934810B1
公开(公告)日：2005-08-23
申请号：US10255276
申请日：2002-09-26
申请人： James A. Williams , Robert H. Andrighetti , Kelvin S. Vartti , David P. Williams
发明人： James A. Williams , Robert H. Andrighetti , Kelvin S. Vartti , David P. Williams
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0804 , G06F12/0891
摘要： A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated if the associated data signals are considered “leaky”. These data signals are flushed from the cache memory after a predetermined delay has occurred. The delay is provided to allow the IP to complete any subsequent requests for the same data before the flush operation is performed, thereby preventing memory thrashing. Pre-fetch logic may also be provided to pre-fetch the data signals associated with the requests. In one embodiment, the rate at which data signals are flushed from cache memory is programmable, and is based on the rate at which requests are processing for pre-fetch purposes.
摘要翻译：提供了一种选择性地从高速缓冲存储器泄漏数据信号的机制。根据本发明的一个方面，指令处理器（IP）被耦合以产生访问高速缓存内的数据信号的请求。一些请求包括泄漏指示符，如果相关的数据信号被认为是“泄漏的”，则会被激活。在发生预定的延迟之后，这些数据信号从高速缓冲存储器中刷新。提供延迟以允许IP在执行刷新操作之前完成对相同数据的任何后续请求，从而防止内存抖动。还可以提供预取逻辑以预取与请求相关联的数据信号。在一个实施例中，数据信号从高速缓存存储器刷新的速率是可编程的，并且基于请求正在处理以用于预取目的的速率。

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