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1. 发明授权

US06751756B1 First level cache parity error inject 失效
标题翻译：第一级缓存奇偶校验错误注入
公开(公告)号：US06751756B1
公开(公告)日：2004-06-15
申请号：US09727610
申请日：2000-12-01
申请人： Thomas D. Hartnett , John Steven Kuslak , Douglas A. Fuller
发明人： Thomas D. Hartnett , John Steven Kuslak , Douglas A. Fuller
IPC分类号： G06F1100
CPC分类号： G06F11/1064 , G06F9/30145 , G06F9/3861 , G06F11/2215 , G06F12/0802 , G11C29/02
摘要： A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.
摘要翻译：一种用于当将指令从读缓冲器复制到第一级高速缓存时，将奇偶校验错误选择性地注入数据处理系统的指令的系统和方法。根据可编程指示器选择性地注入奇偶校验错误，每个可编程指示符与存储在读缓冲器中的一个或多个指令相关联。错误注入系统还包括可编程操作模式，从而在例如从读缓冲器到第一级高速缓存的每个副本期间进行错误注入，或者在仅选择的回写序列期间将发生错误注入。该系统允许对指令处理器中的错误检测和恢复逻辑进行全面测试，并且还允许对与从第二级高速缓存或存储设备执行数据重新获取相关联的逻辑的全面测试。

2. 发明授权

US5872910A Parity-error injection system for an instruction processor 失效
标题翻译：用于指令处理器的奇偶错误注入系统
公开(公告)号：US5872910A
公开(公告)日：1999-02-16
申请号：US777221
申请日：1996-12-27
申请人： John Steven Kuslak , Gary John Lucas , Nguyen Thai Tran
发明人： John Steven Kuslak , Gary John Lucas , Nguyen Thai Tran
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/2236
摘要： A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.
摘要翻译：在从存储设备取出指令并且驻留在数据处理系统中的指令处理器内之前，将奇偶校验错误选择性地注入到指令中的系统和方法。根据可编程指示器选择性地注入奇偶校验错误，每个可编程指示符与存储在存储设备中的一个或多个指令相关联。误差注入系统还包括可编程操作模式，由此在每次取出相关联的指令之后，或者替换地，在相关联的指令的交替取出之后将发生错误注入。该系统允许对指令处理器中的错误检测和恢复逻辑的全面测试，并且还允许对与从存储设备执行数据重新获取相关联的逻辑的全面测试。

3. 发明授权

US07114063B1 Condition indicator for use by a conditional branch instruction 有权
标题翻译：条件分支指令使用的条件指示符
公开(公告)号：US07114063B1
公开(公告)日：2006-09-26
申请号：US09727744
申请日：2000-12-01
申请人： Lawrence Richard Fontaine , John Steven Kuslak , Gary John Lucas , Michael David Pelarski
发明人： Lawrence Richard Fontaine , John Steven Kuslak , Gary John Lucas , Michael David Pelarski
IPC分类号： G06F9/44
CPC分类号： G06F9/3844 , G06F9/30094 , G06F9/3867 , G06F9/3873
摘要： A branch prediction method and system are provided that accurately predict a branch condition early in an instruction pipeline of a data processing system. By accurately predicting the branch condition, the correct target instruction can be fetched early, thereby avoiding many of the inefficiencies associated with branch mispredictions. To accurately predict if a branch condition is satisfied, one or more pre-calculated status bits are stored along with a digital value that is read by the conditional branch instruction to determine if the branch condition is satisfied. By including such a status bit, the condition of the conditional branch instruction may be immediately determined, without waiting for the instruction to be processed by an arithmetic unit or the like in a subsequent pipeline stage.
摘要翻译：提供了一种分支预测方法和系统，其在数据处理系统的指令流水线中提前准确预测分支条件。通过准确预测分支条件，可以提前获取正确的目标指令，从而避免与分支错误预测相关的许多低效率。为了准确地预测分支条件是否满足，一个或多个预先计算的状态位与由条件转移指令读取的数字值一起存储以确定分支条件是否满足。通过包括这样的状态位，可以立即确定条件转移指令的条件，而不必等待在随后的流水线级中由算术单元等处理的指令。

4. 发明授权

US5911083A Programmable processor execution rate controller 失效
标题翻译：可编程处理器执行速率控制器
公开(公告)号：US5911083A
公开(公告)日：1999-06-08
申请号：US777214
申请日：1996-12-27
申请人： John Steven Kuslak
发明人： John Steven Kuslak
IPC分类号： G06F5/06 , G06F9/38
CPC分类号： G06F9/3836 , G06F5/06 , G06F9/3859 , G06F9/3869
摘要： A system and method for controlling the execution rate of an instruction processor on an instruction-by-instruction basis in a data processing system. The user controls the execution rate by specifying "cycle-slip" data for each instruction type in the instruction set. This cycle-slip data is used to force the instruction processor to idle for the specified number of execution cycles during the execution of the associated instruction type, thereby slowing down the rate of execution. Allowing rate control data to be unique for each instruction type allows temporary fixes to be implemented when timing-related hardware problems are discovered during system test. If desired, a uniform number of cycle slips can be imposed on all instructions so that the overall rate of the instruction processor is tailored to match the execution rate of slower peripheral devices.
摘要翻译：一种用于在数据处理系统中逐个指令地控制指令处理器的执行速率的系统和方法。用户通过为指令集中的每个指令类型指定“周期滑移”数据来控制执行率。该循环滑动数据用于在执行相关联的指令类型期间迫使指令处理器空转指定数量的执行周期，从而减慢执行速率。允许速率控制数据对于每种指令类型是唯一的，允许在系统测试期间发现与时序相关的硬件问题时实现临时修复。如果需要，可以对所有指令施加统一数量的循环滑移，使得指令处理器的总速率被调整以匹配较慢的外围设备的执行速率。

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