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1. 发明申请

US20070260962A1 Methods and apparatus for a memory device with self-healing reference bits 有权
标题翻译：具有自修复参考位的存储器件的方法和装置
公开(公告)号：US20070260962A1
公开(公告)日：2007-11-08
申请号：US11416850
申请日：2006-05-02
申请人： Loren Wise , Thomas Andre , Mark Durlam , Eric Salter
发明人： Loren Wise , Thomas Andre , Mark Durlam , Eric Salter
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1008 , G11C11/16
摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
摘要翻译：诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

2. 发明申请

US20070190669A1 Method of manufacturing a magnetoelectronic device 有权
标题翻译：制造磁电子器件的方法
公开(公告)号：US20070190669A1
公开(公告)日：2007-08-16
申请号：US11351610
申请日：2006-02-10
申请人： Mark Durlam , Gloria Kerszykowski , Nicholas Rizzo , Eric Salter , Loren Wise
发明人： Mark Durlam , Gloria Kerszykowski , Nicholas Rizzo , Eric Salter , Loren Wise
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.
摘要翻译：制造磁电子器件的方法包括提供导电材料和与导电材料的至少一部分相邻的电绝缘材料，以及将磁性材料注入到电绝缘材料中。磁性材料增加了电绝缘材料的磁导率。植入物可以是毯子或靶向植入物。

3. 发明申请

US20050122772A1 MRAM device integrated with other types of circuitry 有权
标题翻译：与其他类型电路集成的MRAM器件
公开(公告)号：US20050122772A1
公开(公告)日：2005-06-09
申请号：US10730239
申请日：2003-12-08
申请人： Gloria Kerszykowski , Li Chang , Mark Durlam , Mitchell Lien , Thomas Meixner , Loren Wise
发明人： Gloria Kerszykowski , Li Chang , Mark Durlam , Mitchell Lien , Thomas Meixner , Loren Wise
IPC分类号： G11C11/15 , G11C11/14
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) is embedded with another circuit type. Logic, such as a processing unit, is particularly well-suited circuit type for embedding with MRAM. The embedding is made more efficient by using a metal layer that is used as part of the interconnect for the other circuit also as part of the MRAM cell. The MRAM cells are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic.
摘要翻译：磁阻随机存取存储器（MRAM）嵌入另一种电路类型。诸如处理单元之类的逻辑特别适用于用MRAM嵌入的电路类型。通过使用金属层作为MRAM单元的一部分，作为用于另一电路的互连部分的金属层，使嵌入更加有效。 MRAM单元全部由程序行写入，它们是用于定义要写入的单元格的两条线。因此，简化了设计，因为对于用于MRAM的程序行之一和用于逻辑的互连线之一的金属线的使用是共同的。

4. 发明申请

US20060088947A1 Magnetoresistive random access memory device structures and methods for fabricating the same 有权
公开(公告)号：US20060088947A1
公开(公告)日：2006-04-27
申请号：US10977003
申请日：2004-10-27
申请人： Mitchell Lien , Mark Durlam , Thomas Meixner , Loren Wise
发明人： Mitchell Lien , Mark Durlam , Thomas Meixner , Loren Wise
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L21/76834 , H01L21/76841 , H01L21/76843
摘要： Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

5. 发明申请

US20070045759A1 Passive elements in MRAM embedded integrated circuits 有权
公开(公告)号：US20070045759A1
公开(公告)日：2007-03-01
申请号：US11217146
申请日：2005-08-31
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： H01L43/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

6. 发明申请

US20070002609A1 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US20070002609A1
公开(公告)日：2007-01-04
申请号：US11170874
申请日：2005-06-30
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： G11C11/14
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

7. 发明申请

US20070097732A1 MAGNETIC TUNNEL JUNCTION CURRENT SENSORS 有权
公开(公告)号：US20070097732A1
公开(公告)日：2007-05-03
申请号：US11262053
申请日：2005-10-28
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric salter , Jiang-Kai Zuo
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric salter , Jiang-Kai Zuo
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： An integrated circuit device is provided which includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may comprise a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.
摘要翻译：提供一种集成电路装置，其包括有源电路部件和电流传感器。有源电路组件可以耦合在第一导电层和第二导电层之间，并且被配置为产生第一电流。电流传感器设置在有源电路部件上。电流传感器可以包括设置在第一导电层和第二导电层之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

8. 发明申请

US20050152183A1 MRAM architecture with electrically isolated read and write circuitry 有权
公开(公告)号：US20050152183A1
公开(公告)日：2005-07-14
申请号：US11076523
申请日：2005-03-09
申请人： Joseph Nahas , Thomas Andre , Chitra Subramanian , Bradley Garni , Mark Durlam
发明人： Joseph Nahas , Thomas Andre , Chitra Subramanian , Bradley Garni , Mark Durlam
IPC分类号： G11C11/16 , G11C11/14
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

9. 发明申请

US20070077664A1 Magnetic tunnel junction temperature sensors and methods 失效
标题翻译：磁隧道结温度传感器及方法
公开(公告)号：US20070077664A1
公开(公告)日：2007-04-05
申请号：US11239884
申请日：2005-09-30
申请人： Young Chung , Robert Baird , Mark Durlam
发明人： Young Chung , Robert Baird , Mark Durlam
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L27/228 , G01K7/36 , Y10T428/1114
摘要： Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.
摘要翻译：提供了感测设置在集成电路的基板中的热源的温度的技术。根据一个示例性方法，在热源上提供磁隧道结（“MTJ”）温度传感器。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。然后，MTJ芯的电流的值可以与热源的相应温度相关联。

10. 发明申请

US20060170068A1 MAGNETOELECTRONIC DEVICES UTILIZING PROTECTIVE CAPPING LAYERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：使用保护层的磁电装置及其制造方法
公开(公告)号：US20060170068A1
公开(公告)日：2006-08-03
申请号：US11048015
申请日：2005-01-31
申请人： J. Ren , Brian Butcher , Mark Durlam , Gregory Grynkewich
发明人： J. Ren , Brian Butcher , Mark Durlam , Gregory Grynkewich
IPC分类号： H01L43/00 , H01L29/82
CPC分类号： H01L43/12 , H01L27/228
摘要： Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.
摘要翻译：提供了磁电子器件结构及其制造方法。一种方法包括形成第一和第二导体。第一导体电耦合到互连叠层。沉积在第一导体和第二导体上的第一绝缘层。蚀刻通孔以基本上暴露第一导体。通过无孔沉积在通孔内沉积保护性覆盖层并电耦合到第一导体。磁通存储元件层形成在通孔内并覆盖第二绝缘层和第二导体。

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