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1. 发明授权

US09076837B2 Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage 有权
标题翻译：具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
公开(公告)号：US09076837B2
公开(公告)日：2015-07-07
申请号：US13543662
申请日：2012-07-06
申请人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
发明人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
IPC分类号： H01L29/49 , H01L29/739 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/66325 , H01L21/8222 , H01L29/0634 , H01L29/0696 , H01L29/0808 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66931 , H01L29/7393 , H01L29/7394 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
摘要翻译：本公开提供了金属氧化物半导体横向扩散器件（HV LDMOS），特别是横向绝缘栅双极结型晶体管（LIGBT）及其制造方法。该器件包括具有漂移区的漂移区绝缘体（SOI）衬底，漂移区中的两个相对掺杂的阱区，漂移区和第二阱区中的两个绝缘结构，第二阱区，栅极结构和源极在第二阱区域中的第三阱区域中嵌入第二阱区域。第三阱区域设置在栅极结构和第二绝缘结构之间。

2. 发明授权

US08884405B2 Passivation scheme 有权
标题翻译：钝化方案
公开(公告)号：US08884405B2
公开(公告)日：2014-11-11
申请号：US13539160
申请日：2012-06-29
申请人： Cheng-Chi Chuang , Kun-Ming Huang , Hsuan-Hui Hung , Ming-Yi Lin
发明人： Cheng-Chi Chuang , Kun-Ming Huang , Hsuan-Hui Hung , Ming-Yi Lin
IPC分类号： H01L23/58
CPC分类号： H01L21/02271 , H01L21/02164 , H01L21/0217 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.
摘要翻译：集成电路包括衬底和钝化层。钝化层包括在用于钝化的衬底上形成的底部电介质层，在用于钝化的底部电介质层上形成的掺杂电介质层，以及形成在掺杂介质层上用于钝化的顶部电介质层。

3. 发明授权

US08246214B2 Lamp holder 失效
标题翻译：灯具支架
公开(公告)号：US08246214B2
公开(公告)日：2012-08-21
申请号：US12749038
申请日：2010-03-29
申请人： Kun-Ming Huang , Wei-Chih Hsu
发明人： Kun-Ming Huang , Wei-Chih Hsu
IPC分类号： F21V29/00
CPC分类号： F28F7/00
摘要： A lamp holder includes a heat dissipating seat having a compartment. A substrate is mounted in the compartment of the heat dissipating seat. The substrate includes a control circuit and at least one slot. At least one lighting element is mounted in the at least one slot and in electrical connection with the control circuit. The substrate further includes two flexible terminals in electrical connection with the control circuit and the at least one slot. When mounting the lamp holder into a space of a base, the flexible terminals are inserted into two coupling holes in a conductive portion of an inner periphery of the space. The heat dissipating seat is then pressed downward so that the resiliency of the flexible terminals urges the heat dissipating seat into the space of the base, providing easy assembly.
摘要翻译：灯座包括具有隔间的散热座。衬底安装在散热座的隔室中。衬底包括控制电路和至少一个槽。至少一个照明元件安装在所述至少一个槽中并且与所述控制电路电连接。衬底还包括与控制电路和至少一个槽电连接的两个柔性端子。当将灯座安装到基座的空间中时，柔性端子插入到空间的内周的导电部分中的两个连接孔中。然后向下按压散热座，使得柔性端子的弹性将散热座推向基座的空间，提供容易的组装。

4. 发明授权

US08766357B2 Apparatus and method for high voltage MOS transistor 有权
标题翻译：高压MOS晶体管的装置和方法
公开(公告)号：US08766357B2
公开(公告)日：2014-07-01
申请号：US13410135
申请日：2012-03-01
申请人： Chao-Wei Tseng , Kun-Ming Huang , Cheng-Chi Chuang , Fu-Hsiung Yang
发明人： Chao-Wei Tseng , Kun-Ming Huang , Cheng-Chi Chuang , Fu-Hsiung Yang
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/404 , H01L29/41758 , H01L29/42368 , H01L29/7816
摘要： A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.
摘要翻译：高压MOS晶体管包括在衬底上形成的第一漏极/源极区域，形成在衬底上的第二漏极/源极区域和形成在衬底上的第一金属层。第一金属层包括通过第一金属插塞耦合到第一漏极/源极区域的第一导体，通过第二金属插塞耦合到第二漏极/源极区域的第二导体和形成在第一导体之间的多个浮动金属环和第二导体。浮动金属环有助于提高高压MOS晶体管的击穿电压。

5. 发明申请

US20130228873A1 Apparatus and Method for High Voltage MOS Transistor 有权
标题翻译：高压MOS晶体管的装置和方法
公开(公告)号：US20130228873A1
公开(公告)日：2013-09-05
申请号：US13410135
申请日：2012-03-01
申请人： Chao-Wei Tseng , Kun-Ming Huang , Cheng-Chi Chuang , Fu-Hsiung Yang
发明人： Chao-Wei Tseng , Kun-Ming Huang , Cheng-Chi Chuang , Fu-Hsiung Yang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/404 , H01L29/41758 , H01L29/42368 , H01L29/7816
摘要： A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.
摘要翻译：高压MOS晶体管包括在衬底上形成的第一漏极/源极区域，形成在衬底上的第二漏极/源极区域和形成在衬底上的第一金属层。第一金属层包括通过第一金属插塞耦合到第一漏极/源极区域的第一导体，通过第二金属插塞耦合到第二漏极/源极区域的第二导体和形成在第一导体之间的多个浮动金属环和第二导体。浮动金属环有助于提高高压MOS晶体管的击穿电压。

6. 发明申请

US20060197091A1 Pyramid-shaped capacitor structure 有权
标题翻译：金字塔形电容器结构
公开(公告)号：US20060197091A1
公开(公告)日：2006-09-07
申请号：US11252328
申请日：2005-10-17
申请人： Kun-Ming Huang , YJ Wang , Ying-De Chen , Eugene Chu , Fu-Hsin Chen , Tzu-Yang Wu
发明人： Kun-Ming Huang , YJ Wang , Ying-De Chen , Eugene Chu , Fu-Hsin Chen , Tzu-Yang Wu
IPC分类号： H01L27/108 , H01L29/786 , H01L21/8238 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/60
摘要： A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.
摘要翻译：公开了一种电容器结构，其具有通常为锥形或阶梯形轮廓以防止或减少介电层击穿。电容器结构包括第一导电层，至少一个电介质层，其具有设置在第一导电层上的第一区域和设置在至少一个电介质层上的第二导电层。第二导电层具有小于至少一个电介质层的第一区域的第二区域。还公开了一种制造电容器结构的方法。

7. 发明授权

US06479376B1 Process improvement for the creation of aluminum contact bumps 有权
标题翻译：制造铝接触凸块的工艺改进
公开(公告)号：US06479376B1
公开(公告)日：2002-11-12
申请号：US09808925
申请日：2001-03-16
申请人： Kun-Ming Huang , Cheng-Wei Lee , Ding-Jeng Yu
发明人： Kun-Ming Huang , Cheng-Wei Lee , Ding-Jeng Yu
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05147 , H01L2224/05171 , H01L2224/05573 , H01L2224/0558 , H01L2224/13099 , H01L2224/13124 , H01L2224/45144 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/05647
摘要： A new method is provided for the creation of an aluminum bump on a surface of a semiconductor device. A patterned layer of aluminum overlying a substrate is created, the patterned layer of aluminum is the layer of aluminum over which a contact bump is to be created. A layer of passivation is deposited, a first layer of photoresist is deposited for the creation of an opening in the layer of passivation that partially exposed the surface of the patterned layer of aluminum. This patterned first layer of photoresist remains in place, a layer of aluminum is sputter deposited, a second layer of photoresist is deposited which is patterned and etched for the creation of the aluminum bump overlying the patterned layer of aluminum. The aluminum solder bump is created by etching the deposited layer of aluminum. After the solder bump has been created, the patterned first and the second layers of photoresist are removed in one processing step, leaving in place the solder bump.
摘要翻译：提供了一种在半导体器件的表面上形成铝凸块的新方法。产生覆盖在衬底上的图案化的铝层，铝的图案化层是铝层，将在其上形成接触凸块。沉积一层钝化物，沉积第一层光致抗蚀剂，以在钝化层中形成一部分露出图案化的铝层的表面的开口。该图案化的第一层光致抗蚀剂保持在适当位置，溅射沉积一层铝，沉积第二层光致抗蚀剂，其被图案化和蚀刻，以形成覆盖图案化的铝层的铝凸块。铝焊料凸块通过蚀刻沉积的铝层而产生。在产生焊料凸点之后，在一个处理步骤中去除图案化的第一和第二层光致抗蚀剂，留下焊料凸点。

8. 发明授权

US07221039B2 Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer 有权
标题翻译：薄膜晶体管（TFT）器件结构采用富硅氧化物钝化层
公开(公告)号：US07221039B2
公开(公告)日：2007-05-22
申请号：US10876010
申请日：2004-06-24
申请人： Kun-Ming Huang , Cheng-Fu Hsu
发明人： Kun-Ming Huang , Cheng-Fu Hsu
IPC分类号： H01L23/58
CPC分类号： H01L29/66765 , H01L27/1248 , H01L29/78669 , H01L29/78678
摘要： A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of a silicon rich silicon oxide material formed over the thin film transistor device. The passivation layer formed of the silicon rich silicon oxide material provides the thin film transistor device with enhanced performance.
摘要翻译：薄膜晶体管器件结构和制造薄膜晶体管器件结构的方法各自包括在衬底上形成的薄膜晶体管器件。薄膜晶体管器件结构还包括由形成在薄膜晶体管器件上的富硅氧化物材料形成的钝化层。由富硅氧化物材料形成的钝化层提供具有增强性能的薄膜晶体管器件。

9. 发明授权

US07109090B1 Pyramid-shaped capacitor structure 有权
标题翻译：金字塔形电容器结构
公开(公告)号：US07109090B1
公开(公告)日：2006-09-19
申请号：US11074523
申请日：2005-03-07
申请人： Kun-Ming Huang , Yeh-Jye Wann
发明人： Kun-Ming Huang , Yeh-Jye Wann
IPC分类号： H01L21/8242
CPC分类号： H01L28/60
摘要： A capacitor structure which has a generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.
摘要翻译：公开了一种电容器结构，其具有大致金字塔形或台阶状以防止或减少介电层击穿。电容器结构包括第一导电层，至少一个电介质层，其具有设置在第一导电层上的第一区域和设置在至少一个电介质层上的第二导电层。第二导电层具有小于至少一个电介质层的第一区域的第二区域。还公开了一种制造电容器结构的方法。

10. 发明授权

US07888767B2 Structures of high-voltage MOS devices with improved electrical performance 有权
标题翻译：具有改善电气性能的高压MOS器件的结构
公开(公告)号：US07888767B2
公开(公告)日：2011-02-15
申请号：US11588902
申请日：2006-10-26
申请人： Kun-Ming Huang , Hsueh-Liang Chou , Weng-Chu Chu , Chen-Bau Wu
发明人： Kun-Ming Huang , Hsueh-Liang Chou , Weng-Chu Chu , Chen-Bau Wu
IPC分类号： H01L29/02
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7833
摘要： A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括覆盖衬底的第一导电类型的第一高电压阱（HVW）区域，覆盖衬底并横向邻接第一HVW区域的与第一导电类型相反的第二导电类型的第二HVW区域，以及位于第二HVW区域的第二导电类型的第三HVW区域。第一HVW区域下方的区域基本上没有第三HVW区域，其中第三HVW区域具有比第一HVW区域的底部低的底部。该半导体结构还包括一部分中的绝缘区域并从第一HVW区域的顶表面延伸到第一HVW区域，从第一HVW区域延伸到第二HVW区域上方的栅极电介质，其中栅极电介质具有绝缘区域上的栅极电极和栅极电介质上的栅电极。

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