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1. 发明授权

US06479376B1 Process improvement for the creation of aluminum contact bumps 有权
标题翻译：制造铝接触凸块的工艺改进
公开(公告)号：US06479376B1
公开(公告)日：2002-11-12
申请号：US09808925
申请日：2001-03-16
申请人： Kun-Ming Huang , Cheng-Wei Lee , Ding-Jeng Yu
发明人： Kun-Ming Huang , Cheng-Wei Lee , Ding-Jeng Yu
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05147 , H01L2224/05171 , H01L2224/05573 , H01L2224/0558 , H01L2224/13099 , H01L2224/13124 , H01L2224/45144 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/05647
摘要： A new method is provided for the creation of an aluminum bump on a surface of a semiconductor device. A patterned layer of aluminum overlying a substrate is created, the patterned layer of aluminum is the layer of aluminum over which a contact bump is to be created. A layer of passivation is deposited, a first layer of photoresist is deposited for the creation of an opening in the layer of passivation that partially exposed the surface of the patterned layer of aluminum. This patterned first layer of photoresist remains in place, a layer of aluminum is sputter deposited, a second layer of photoresist is deposited which is patterned and etched for the creation of the aluminum bump overlying the patterned layer of aluminum. The aluminum solder bump is created by etching the deposited layer of aluminum. After the solder bump has been created, the patterned first and the second layers of photoresist are removed in one processing step, leaving in place the solder bump.
摘要翻译：提供了一种在半导体器件的表面上形成铝凸块的新方法。产生覆盖在衬底上的图案化的铝层，铝的图案化层是铝层，将在其上形成接触凸块。沉积一层钝化物，沉积第一层光致抗蚀剂，以在钝化层中形成一部分露出图案化的铝层的表面的开口。该图案化的第一层光致抗蚀剂保持在适当位置，溅射沉积一层铝，沉积第二层光致抗蚀剂，其被图案化和蚀刻，以形成覆盖图案化的铝层的铝凸块。铝焊料凸块通过蚀刻沉积的铝层而产生。在产生焊料凸点之后，在一个处理步骤中去除图案化的第一和第二层光致抗蚀剂，留下焊料凸点。

2. 发明授权

US07880234B2 NPN Darlington ESD protection circuit 有权
标题翻译： NPN达林顿ESD保护电路
公开(公告)号：US07880234B2
公开(公告)日：2011-02-01
申请号：US11463002
申请日：2006-08-07
申请人： Tao Cheng , Ding-Jeng Yu
发明人： Tao Cheng , Ding-Jeng Yu
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L27/0259
摘要： An electrostatic discharge protection circuit includes a metal-oxide semiconductor transistor having a first terminal connected to an input end, and a gate connected to a supply voltage; a first bipolar junction transistor having a first terminal connected to the input end, and a base connected to a second terminal of the metal-oxide semiconductor transistor; a second bipolar junction transistor having a first terminal connected to the input end, a second terminal connected to the supply voltage, and a base connected to the second terminal of the first bipolar junction transistor; a first resistive device having a first end connected to the second terminal of the metal-oxide semiconductor transistor, and a second end connected to the supply voltage; and a second resistive device having a first end connected to the second terminal of the first bipolar junction transistor, and a second end connected to the supply voltage.
摘要翻译：静电放电保护电路包括具有连接到输入端的第一端子和连接到电源电压的栅极的金属氧化物半导体晶体管; 第一双极结型晶体管，其具有连接到所述输入端的第一端子和与所述金属氧化物半导体晶体管的第二端子连接的基极; 第二双极结晶体管，其具有连接到输入端的第一端子，连接到电源电压的第二端子和连接到第一双极结型晶体管的第二端子的基极; 第一电阻器件，其具有连接到所述金属氧化物半导体晶体管的第二端子的第一端和连接到所述电源电压的第二端; 以及第二电阻器件，其具有连接到第一双极结型晶体管的第二端子的第一端和连接到电源电压的第二端。

3. 发明申请

US20070020818A1 ESD protection device in high voltage and manufacturing method for the same 有权
标题翻译： ESD保护器件在高压及制造方法相同
公开(公告)号：US20070020818A1
公开(公告)日：2007-01-25
申请号：US11186857
申请日：2005-07-22
申请人： Ding-Jeng Yu , Tao Cheng , Chao-Chih Chiu
发明人： Ding-Jeng Yu , Tao Cheng , Chao-Chih Chiu
IPC分类号： H01L21/82 , H01L21/331 , H01L21/8222
CPC分类号： H01L27/0259 , H01L27/0664
摘要： Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one PNP transistor and at least one diode connected in parallel, and an ESD discharging path is formed thereby. The PNP transistor is formed with an adjacent heavily doped P-type semiconductor zone (P+), lightly doped N-type semiconductor zone (N−), and a P-type semiconductor substrate. The diode is formed with an adjacent lightly doped N-type semiconductor zone and a light doped P-type semiconductor zone.
摘要翻译：公开了高压静电放电（ESD）保护装置及相关制造方法。上述ESD保护装置被设置成桥接地面和与要保护的内部电路连接的输入。其中，用于高电压的ESD保护装置包括至少一个PNP晶体管和至少一个二极管并联，并且由此形成ESD放电路径。 PNP晶体管形成有相邻的重掺杂P型半导体区（P +），轻掺杂的N型半导体区（N）和P型半导体衬底。二极管形成有相邻的轻掺杂N型半导体区和掺杂P型半导体区。

4. 发明授权

US07491584B2 ESD protection device in high voltage and manufacturing method for the same 有权
标题翻译： ESD保护器件在高压及制造方法相同
公开(公告)号：US07491584B2
公开(公告)日：2009-02-17
申请号：US11186857
申请日：2005-07-22
申请人： Ding-Jeng Yu , Tao Cheng , Chao-Chih Chiu
发明人： Ding-Jeng Yu , Tao Cheng , Chao-Chih Chiu
IPC分类号： H01L21/82 , H01L21/8222 , H01L21/8228
CPC分类号： H01L27/0259 , H01L27/0664
摘要： Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one PNP transistor and at least one diode connected in parallel, and an ESD discharging path is formed thereby. The PNP transistor is formed with an adjacent heavily doped P-type semiconductor zone (P+), lightly doped N-type semiconductor zone (N−), and a P-type semiconductor substrate. The diode is formed with an adjacent lightly doped N-type semiconductor zone and a light doped P-type semiconductor zone.
摘要翻译：公开了高压静电放电（ESD）保护装置及相关制造方法。上述ESD保护装置被设置成桥接地面和与要保护的内部电路连接的输入。其中，用于高电压的ESD保护装置包括至少一个PNP晶体管和至少一个二极管并联，并且由此形成ESD放电路径。 PNP晶体管形成有相邻的重掺杂P型半导体区（P +），轻掺杂的N型半导体区（N）和P型半导体衬底。二极管形成有相邻的轻掺杂N型半导体区和掺杂P型半导体区。

5. 发明授权

US07203050B2 NPN Darlington ESD protection circuit 有权
标题翻译： NPN达林顿ESD保护电路
公开(公告)号：US07203050B2
公开(公告)日：2007-04-10
申请号：US10604354
申请日：2003-07-14
申请人： Tao Cheng , Ding-Jeng Yu
发明人： Tao Cheng , Ding-Jeng Yu
IPC分类号： H02H3/22
CPC分类号： H01L27/0266 , H01L27/0259
摘要： An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor is connected to the control end of the NPN Darlington circuit. The gate of NMOS transistor is connected to the output end of the NPN Darlington circuit.
摘要翻译：静电放电保护（ESD）电路包括NPN达林顿电路和n型金属氧化物半导体（NMOS）晶体管。 NMOS晶体管的漏极连接到NPN达林顿电路的输入端。 NMOS晶体管的源极连接到NPN达林顿电路的控制端。 NMOS晶体管的栅极连接到NPN达林顿电路的输出端。

6. 发明授权

US08044466B2 ESD protection device in high voltage and manufacturing method for the same 有权
标题翻译： ESD保护器件在高压及制造方法相同
公开(公告)号：US08044466B2
公开(公告)日：2011-10-25
申请号：US12352407
申请日：2009-01-12
申请人： Ding-Jeng Yu , Tao Cheng , Chao-Chih Chiu
发明人： Ding-Jeng Yu , Tao Cheng , Chao-Chih Chiu
IPC分类号： H01L23/62
CPC分类号： H01L27/0259 , H01L27/0664
摘要： An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the substrate having a first terminal of the first conductive type and a second terminal of the second conductive type, wherein the input terminal and the second terminal are coupled to an input, and the ground terminal and the first terminal are coupled to a ground.
摘要翻译： ESD保护器件包括第一导电类型的衬底; 形成在所述基板中的晶体管具有所述第一导电类型的输入端子，第二导电类型的控制端子和所述第一导电类型的接地端子; 以及形成在所述基板中的二极管，其具有所述第一导电类型的第一端子和所述第二导电类型的第二端子，其中所述输入端子和所述第二端子耦合到输入端，并且所述接地端子和所述第一端子耦合到地面

7. 发明申请

US20060267102A1 NPN DARLINGTON ESD PROTECTION CIRCUIT 有权
标题翻译： NPN达林顿ESD保护电路
公开(公告)号：US20060267102A1
公开(公告)日：2006-11-30
申请号：US11463002
申请日：2006-08-07
申请人： Tao Cheng , Ding-Jeng Yu
发明人： Tao Cheng , Ding-Jeng Yu
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L27/0259
摘要： An electrostatic discharge protection circuit includes a metal-oxide semiconductor transistor having a first terminal connected to an input end, and a gate connected to a supply voltage; a first bipolar junction transistor having a first terminal connected to the input end, and a base connected to a second terminal of the metal-oxide semiconductor transistor; a second bipolar junction transistor having a first terminal connected to the input end, a second terminal connected to the supply voltage, and a base connected to the second terminal of the first bipolar junction transistor; a first resistive device having a first end connected to the second terminal of the metal-oxide semiconductor transistor, and a second end connected to the supply voltage; and a second resistive device having a first end connected to the second terminal of the first bipolar junction transistor, and a second end connected to the supply voltage.
摘要翻译：静电放电保护电路包括具有连接到输入端的第一端子和连接到电源电压的栅极的金属氧化物半导体晶体管; 第一双极结型晶体管，其具有连接到所述输入端的第一端子和与所述金属氧化物半导体晶体管的第二端子连接的基极; 第二双极结晶体管，其具有连接到输入端的第一端子，连接到电源电压的第二端子和连接到第一双极结型晶体管的第二端子的基极; 第一电阻器件，其具有连接到所述金属氧化物半导体晶体管的第二端子的第一端和连接到所述电源电压的第二端; 以及第二电阻器件，其具有连接到第一双极结型晶体管的第二端子的第一端和连接到电源电压的第二端。

8. 发明授权

US6130149A Approach for aluminum bump process 有权
标题翻译：铝凸块加工方法
公开(公告)号：US6130149A
公开(公告)日：2000-10-10
申请号：US374298
申请日：1999-08-16
申请人： Wen-Chen Chien , Chi-Hsin Lo , Ding-Jeng Yu
发明人： Wen-Chen Chien , Chi-Hsin Lo , Ding-Jeng Yu
IPC分类号： C23C8/10 , C23C8/36 , H01L21/60 , C23C3/02 , H01L21/283
CPC分类号： H01L24/11 , C23C8/10 , C23C8/36 , H01L2224/05001 , H01L2224/05022 , H01L2224/05571 , H01L2224/056 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13015 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , Y10S438/97
摘要： A method is disclosed for forming an aluminum bump on an integrated circuit (IC) chip without leaving any metal residue on the passivation layer of the chip. This is accomplished by planarizing the passivation layer with spin-on-glass (SOG) and then forming a PECVD oxide as a sacrificial layer over the SOG, and etching through these layers to form an opening over a metal pad underlying the passivation layer. Then, a layer of aluminum is deposited over the substrate, including the opening, to form an aluminum bump. Aluminum bump is next formed by etching through a patterned oxide which acts as a hard mask over the aluminum layer. The SOG is then removed leaving the passivation layer free of any aluminum residue.
摘要翻译：公开了一种用于在集成电路（IC）芯片上形成铝凸块而不在芯片的钝化层上留下任何金属残留物的方法。这通过用旋涂玻璃（SOG）平坦化钝化层，然后在SOG上形成作为牺牲层的PECVD氧化物，并通过这些层蚀刻以在钝化层下方的金属焊盘上形成开口来实现。然后，在基板上沉积一层铝，包括开口，以形成铝凸块。接下来通过蚀刻通过在铝层上作为硬掩模的图案化氧化物形成铝凸块。然后除去SOG，留下钝化层没有任何铝残留物。

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