专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07888216B2 Method of fabricating a high performance power MOS 有权
标题翻译：制造高性能功率MOS的方法
公开(公告)号：US07888216B2
公开(公告)日：2011-02-15
申请号：US12757242
申请日：2010-04-09
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.
摘要翻译：制造半导体器件的方法包括在衬底中形成包括第一类掺杂剂的阱区; 在所述阱区中形成包含不同于所述第一类型掺杂剂的第二类型掺杂剂的基极区; 以及在包括第一类型掺杂剂的衬底源极和漏极区域中形成。该方法还包括在衬底上形成横向插入在源区和漏区之间的栅电极; 以及在所述衬底上形成栅极间隔件，所述栅极间隔件横向设置在所述源区域和所述栅电极之间，邻近所述栅电极的一侧并且具有嵌入其中的导电特征。阱区域围绕漏极区域和基极区域，并且基极区域部分地设置在围绕源极区域的栅极电极周围，该源极区域限定栅极电极下方的沟道，其长度基本上小于栅电极的长度的一半。

2. 发明申请

US20100006935A1 Breakdown Voltages of Ultra-High Voltage Devices By Forming Tunnels 有权
标题翻译：通过形成隧道的超高压器件的故障电压
公开(公告)号：US20100006935A1
公开(公告)日：2010-01-14
申请号：US12170246
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

3. 发明申请

US20090001462A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20090001462A1
公开(公告)日：2009-01-01
申请号：US12205961
申请日：2008-09-08
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

4. 发明申请

US20080246083A1 Recessed drift region for HVMOS breakdown improvement 有权
标题翻译：嵌入式漂移区，用于HVMOS故障改善
公开(公告)号：US20080246083A1
公开(公告)日：2008-10-09
申请号：US11732468
申请日：2007-04-03
申请人： William Wei-Yuan Tien , Fu-Hsin Chen
发明人： William Wei-Yuan Tien , Fu-Hsin Chen
IPC分类号： H01L29/76 , H01L29/78
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/66659 , H01L29/7834 , H01L29/7835
摘要： A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode.
摘要翻译：提供了具有增加的击穿电压的高压金属氧化物半导体（HVMOS）器件及其形成方法。 HVMOS器件包括半导体衬底; 在所述半导体衬底的表面上的栅极电介质; 栅电极上的栅电极; 与栅电极相邻并水平间隔开的源/漏区; 以及半导体衬底中的凹陷并填充有电介质材料。凹槽位于栅电极和源极/漏极区之间，并且与栅电极水平间隔开。

5. 发明申请

US20070085145A1 High voltage transistor with improved driving current 有权
标题翻译：具有改善驱动电流的高压晶体管
公开(公告)号：US20070085145A1
公开(公告)日：2007-04-19
申请号：US11253919
申请日：2005-10-19
申请人： William Tien , Fu-Hsin Chen , Jui-Wen Lin , You-Kuo Wu
发明人： William Tien , Fu-Hsin Chen , Jui-Wen Lin , You-Kuo Wu
IPC分类号： H01L29/94
CPC分类号： H01L29/66659 , H01L29/7835
摘要： A semiconductor device and its method of manufacture are provided. Embodiments include forming a first doped region and a second doped region. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor. A gate-side boundary of the first doped region underlies part of the gate electrode. The second doped region is formed within the first doped region adjacent the gate electrode. A gate-side boundary of the second doped region is separated from a closest edge of a gate electrode spacer by a first distance. An isolation region-side boundary of the second doped region is separated from a closest edge of a nearest isolation region by a second distance.
摘要翻译：提供半导体器件及其制造方法。实施例包括形成第一掺杂区和第二掺杂区。第一和第二掺杂区域可以形成如HVMOS晶体管中的双扩散漏极结构。第一掺杂区域的栅极侧边界位于栅电极的一部分的下方。第二掺杂区形成在与栅电极相邻的第一掺杂区内。第二掺杂区域的栅极侧边界与栅电极间隔物的最近边缘分开第一距离。第二掺杂区域的隔离区域侧边界与最近隔离区域的最近边缘分开第二距离。

6. 发明授权

US07183171B2 Pyramid-shaped capacitor structure 有权
标题翻译：金字塔形电容器结构
公开(公告)号：US07183171B2
公开(公告)日：2007-02-27
申请号：US11252328
申请日：2005-10-17
申请人： Kun-Ming Huang , YJ Wang , Ying-De Chen , Eugene Chu , Fu-Hsin Chen , Tzu-Yang Wu
发明人： Kun-Ming Huang , YJ Wang , Ying-De Chen , Eugene Chu , Fu-Hsin Chen , Tzu-Yang Wu
IPC分类号： H01L21/8242
CPC分类号： H01L28/60
摘要： A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.
摘要翻译：公开了一种电容器结构，其具有通常为锥形或阶梯形轮廓以防止或减少介电层击穿。电容器结构包括第一导电层，至少一个电介质层，其具有设置在第一导电层上的第一区域和设置在至少一个电介质层上的第二导电层。第二导电层具有小于至少一个电介质层的第一区域的第二区域。还公开了一种制造电容器结构的方法。

7. 发明授权

US07045414B2 Method of fabricating high voltage transistor 有权
标题翻译：制造高压晶体管的方法
公开(公告)号：US07045414B2
公开(公告)日：2006-05-16
申请号：US10723771
申请日：2003-11-26
申请人： Fu-Hsin Chen , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Ruey-Hsin Liu
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L29/66659 , H01L29/0692 , H01L29/7835
摘要： A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped region is formed within the first doped region. A gate-side boundary of the second doped region is separated from a closest edge of the gate electrode by a first spaced distance. The gate-side boundary of the second doped region is separated from a closest edge of the spacer by a second spaced distance. The first spaced distance is greater than the second spaced distance. An isolation-side boundary of the second doped region may be separated from an adjacent isolation structure by a third spaced distance.
摘要翻译：高压MOS晶体管具有热驱动的第一掺杂区域和形成双扩散漏极结构的第二掺杂区域。第一掺杂区域的边界被分级。第一掺杂区的栅极侧边界在栅电极的一部分的横向下方延伸。第二掺杂区域形成在第一掺杂区域内。第二掺杂区域的栅极侧边界与栅电极的最近边缘隔开第一间隔距离。第二掺杂区域的栅极侧边界与间隔物的最近边缘隔开第二间隔距离。第一间隔距离大于第二间隔距离。第二掺杂区域的隔离侧边界可以与相邻隔离结构隔开第三间隔距离。

8. 发明申请

US20050227448A1 High voltage double diffused drain MOS transistor with medium operation voltage 有权
标题翻译：具有中等工作电压的高压双扩散漏极MOS晶体管
公开(公告)号：US20050227448A1
公开(公告)日：2005-10-13
申请号：US10819527
申请日：2004-04-07
申请人： Fu-Hsin Chen , Yi-Chun Lin , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Yi-Chun Lin , Ruey-Hsin Liu
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823418 , H01L29/0692 , H01L29/0847 , H01L29/7835
摘要： A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.
摘要翻译：一种在半导体晶片上制造具有中等工作电压的高压MOS晶体管的方法。晶体管具有双扩散漏极（DDD）和诸如6至10伏特的中等操作电压，这对于具有低和高操作晶体管器件的应用是有利的。 DDD的第二扩散区域与栅极和栅极电介质的侧壁上的间隔物自对准，使得晶体管尺寸可能降低。

9. 发明授权

US08389341B2 Lateral power MOSFET with high breakdown voltage and low on-resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US08389341B2
公开(公告)日：2013-03-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

10. 发明申请

US20120003803A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20120003803A1
公开(公告)日：2012-01-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式