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1. 发明申请

US20070054450A1 Structure and fabrication of an MRAM cell 审中-公开
标题翻译： MRAM单元的结构和制造
公开(公告)号：US20070054450A1
公开(公告)日：2007-03-08
申请号：US11221146
申请日：2005-09-07
申请人： Liubo Hong , Mao-Min Chen , Tai Min , Jun Chen
发明人： Liubo Hong , Mao-Min Chen , Tai Min , Jun Chen
IPC分类号： H01L21/336
CPC分类号： H01L43/12
摘要： MTJ stacks formed using prior art processes often fail because of shorts between the pinned layer and the top electrode. This problem has been overcome by depositing a protective layer on the MTJ sidewalls followed by an inter-layer dielectric. Then planarizing until the protective layer is just exposed. Finally, an etching (or second CMP) process is used to selectively remove the protective layer from the top surface of the cap layer.
摘要翻译：使用现有技术方法形成的MTJ堆叠通常由于被钉扎层和顶部电极之间的短路而失败。通过在MTJ侧壁上沉积保护层，接着是层间电介质来克服这个问题。然后平面化直到保护层刚刚暴露。最后，使用蚀刻（或第二CMP）工艺来从盖层的顶表面选择性地去除保护层。

2. 发明授权

US07217577B2 Structure/method to fabricate a high-performance magnetic tunneling junction MRAM 失效
标题翻译：制造高性能磁隧道结MRAM的结构/方法
公开(公告)号：US07217577B2
公开(公告)日：2007-05-15
申请号：US11522663
申请日：2006-09-18
申请人： Cheng T. Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
发明人： Cheng T. Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L43/08 , Y10S977/934 , Y10S977/935
摘要： An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched capping layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.
摘要翻译：在由溅射蚀刻的Ta层覆盖的导电引线和磁保持层上形成MTJ（磁性隧道结）MRAM（磁性随机存取存储器）单元。作为溅射蚀刻的结果，Ta覆盖层具有光滑的表面，并且光滑表面促进随后形成具有光滑的平坦层和自由基氧化（ROX）Al隧穿势垒层的下电极（钉扎/钉扎层）其超薄，光滑，并具有高击穿电压。在Ta的溅射蚀刻的覆盖层上形成NiCr种子层。在其开关特性，GMR比和结电阻方面，所得到的器件通常具有改进的性能特性。

3. 发明申请

US20060208296A1 Novel structure and method to fabricate high performance MTJ devices for MRAM applications 失效
标题翻译：用于制造用于MRAM应用的高性能MTJ器件的新型结构和方法
公开(公告)号：US20060208296A1
公开(公告)日：2006-09-21
申请号：US11080860
申请日：2005-03-15
申请人： Cheng Horng , Ru-Ying Tong , Mao-Min Chen , Liubo Hong , Min Li
发明人： Cheng Horng , Ru-Ying Tong , Mao-Min Chen , Liubo Hong , Min Li
IPC分类号： H01L29/94
CPC分类号： H01L43/08 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/3163 , G11B5/3906 , H01L43/12
摘要： A high performance MTJ in an MRAM array is disclosed in which the bottom conductor has an amorphous Ta capping layer. A key feature is a surfactant layer comprised of oxygen that is formed on the Ta surface. The resulting smooth and flat Ta capping layer promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-μm2. The MTJ configuraton is extendable to a 0.2×0.4 micron MTJ bit size.
摘要翻译：公开了一种MRAM阵列中的高性能MTJ，其中底部导体具有无定形Ta覆盖层。关键特征是由在Ta表面上形成的氧构成的表面活性剂层。得到的平滑且平坦的Ta覆盖层促进MTJ层中平滑且平坦的表面，随后在表面活性剂层上形成。对于0.3×0.6微米的MTJ位尺寸，35至40埃厚的NiFe（18％）自由层，由9至10埃厚的Al层的ROX氧化产生的AlO x势垒层，以及Ru / Ta / 使用Ru覆盖层来产生大于40％的dR / R和约4000欧姆 - 姆2的RA。 MTJ配置可扩展到0.2x0.4微米的MTJ位大小。

4. 发明授权

US08673654B2 Underlayer for high performance magnetic tunneling junction MRAM 有权
标题翻译：高性能磁隧道结MRAM底层
公开(公告)号：US08673654B2
公开(公告)日：2014-03-18
申请号：US12589465
申请日：2009-10-23
申请人： Liubo Hong , Cheng Horng , Mao-Min Chen , Ru-Yin Tong
发明人： Liubo Hong , Cheng Horng , Mao-Min Chen , Ru-Yin Tong
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G01R33/09 , G01R33/093 , G01R33/098 , G11B5/3906 , G11B5/3909 , G11C11/161 , G11C11/1673 , H01F10/30 , H01F10/3254 , H01F10/3259 , H01F10/3272 , H01F10/3295 , H01F41/307 , H01L43/08 , H01L43/10 , Y10T428/1114
摘要： An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the α-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the α-TaN layer. An α-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an α-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.
摘要翻译：公开了一种MRAM结构，其中底部电极具有无定形TaN覆盖层，以一致地提供在覆盖的MTJ中的AFM，固定，隧道势垒和自由层的平滑且致密的生长。与传统的Ta覆盖层不同，TaN是抗氧化的并且具有高电阻率以避免由于覆盖层在隧道势垒层的侧壁上的再沉积引起的感测电流的分流。或者，α-TaN层是MTJ中的种子层。此外，种子层可以是由α-TaN层上的NiCr，NiFe或NiFeCr层构成的复合层。也可以在TMR读取头中使用α-TaN覆盖层或种子层。在α-TaN覆盖层上形成的MTJ具有高MR比，高Vb和RA，其类似于基于优化的Ta覆盖层的MTJ获得的结果。

5. 发明授权

US07880249B2 Spacer structure in MRAM cell and method of its fabrication 有权
标题翻译： MRAM单元的间隔结构及其制作方法
公开(公告)号：US07880249B2
公开(公告)日：2011-02-01
申请号：US11290763
申请日：2005-11-30
申请人： Jun Yuan , Liubo Hong , Mao-Min Chen
发明人： Jun Yuan , Liubo Hong , Mao-Min Chen
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： Methods are presented for fabricating an MTJ element having a precisely controlled spacing between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not thinned and serves to maintain an exact spacing between the bit line and the MTJ free layer.
摘要翻译：提出了用于制造在其自由层和位线之间具有精确控制的间隔的MTJ元件的方法，此外，具有邻接MTJ元件的侧面形成的保护性间隔层以消除MTJ层与钻头之间的泄漏电流线。每种方法在MTJ元件的侧面上形成电介质间隔层，并且根据该方法，包括在用于形成Cu镶嵌位线的蚀刻工艺期间保护间隔层的附加层。在该过程的各个阶段，还形成介电层以用作CMP停止层，使得MTJ元件上的覆盖层不会通过使周围绝缘平坦化的CMP工艺变薄。在平坦化之后，通过各向异性蚀刻去除停止层，其精度使得MTJ元件覆盖层不变薄并且用于保持位线和MTJ自由层之间的精确间隔。

6. 发明授权

US08422276B2 Spacer structure in MRAM cell and method of its fabrication 有权
标题翻译： MRAM单元的间隔结构及其制作方法
公开(公告)号：US08422276B2
公开(公告)日：2013-04-16
申请号：US12930955
申请日：2011-01-20
申请人： Jun Yuan , Liubo Hong , Mao-Min Chen
发明人： Jun Yuan , Liubo Hong , Mao-Min Chen
IPC分类号： G11C11/00
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer.
摘要翻译：提出了用于制造在其自由层和位线之间具有均匀垂直距离的MTJ元件的方法，此外，具有邻接MTJ元件的侧面形成的保护间隔层，以消除MTJ层与钻头之间的泄漏电流线。每种方法在MTJ元件的侧面上形成电介质间隔层，并且根据该方法，包括在用于形成Cu镶嵌位线的蚀刻工艺期间保护间隔层的附加层。在该过程的各个阶段，还形成介电层以用作CMP停止层，使得MTJ元件上的覆盖层不会通过使周围绝缘平坦化的CMP工艺变薄。在平坦化之后，通过各向异性蚀刻去除停止层，其精度使得MTJ元件覆盖层的厚度不减小并用于保持位线和MTJ自由层之间的均匀垂直距离。

7. 发明授权

US07211447B2 Structure and method to fabricate high performance MTJ devices for MRAM applications 失效
标题翻译：制造用于MRAM应用的高性能MTJ器件的结构和方法
公开(公告)号：US07211447B2
公开(公告)日：2007-05-01
申请号：US11080868
申请日：2005-03-15
申请人： Cheng T. Horng , Ru-Ying Tong , Mao-Min Chen , Liubo Hong , Min Li
发明人： Cheng T. Horng , Ru-Ying Tong , Mao-Min Chen , Liubo Hong , Min Li
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： A method of forming a high performance MTJ in an MRAM array is disclosed. A Ta/Ru capping layer in a bottom conductor is sputter etched to remove the Ru layer and form an amorphous Ta capping layer. A key feature is a subsequent surface treatment of the Ta capping layer in a transient vacuum chamber where a self-annealing occurs and a surfactant layer is formed on the Ta surface. The resulting smooth and flat Ta surface promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-μm2.
摘要翻译：公开了一种在MRAM阵列中形成高性能MTJ的方法。溅射蚀刻底部导体中的Ta / Ru覆盖层以去除Ru层并形成无定形Ta覆盖层。一个关键的特征是在瞬态真空室中Ta覆盖层的后续表面处理，其中发生自退火并且在Ta表面上形成表面活性剂层。所得到的平滑且平坦的Ta表面促进在表面活性剂层上随后形成的MTJ层中的光滑和平坦的表面。对于0.3×0.6微米的MTJ位尺寸，35至40埃厚的NiFe（18％）自由层，由9至10埃厚的Al层的ROX氧化产生的AlO x势垒层，以及Ru / Ta / 使用Ru覆盖层来产生大于40％的dR / R和约4000欧姆 - 姆2的RA。

8. 发明申请

US20070015294A1 Novel structure/method to fabricate a high-performance magnetic tunneling junction MRAM 失效
标题翻译：制造高性能磁隧道结MRAM的新型结构/方法
公开(公告)号：US20070015294A1
公开(公告)日：2007-01-18
申请号：US11522663
申请日：2006-09-18
申请人： Cheng Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
发明人： Cheng Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L43/08 , Y10S977/934 , Y10S977/935
摘要： An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched capping layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.
摘要翻译：在由溅射蚀刻的Ta层覆盖的导电引线和磁保持层上形成MTJ（磁性隧道结）MRAM（磁性随机存取存储器）单元。作为溅射蚀刻的结果，Ta覆盖层具有光滑的表面，并且光滑表面促进随后形成具有光滑的平坦层和自由基氧化（ROX）Al隧穿势垒层的下电极（钉扎/钉扎层）其超薄，光滑，并具有高击穿电压。在Ta的溅射蚀刻的覆盖层上形成NiCr种子层。在其开关特性，GMR比和结电阻方面，所得到的器件通常具有改进的性能特性。

9. 发明申请

US20060211198A1 Novel structure and method to fabricate high performance MTJ devices for MRAM applications 失效
标题翻译：用于制造用于MRAM应用的高性能MTJ器件的新型结构和方法
公开(公告)号：US20060211198A1
公开(公告)日：2006-09-21
申请号：US11080868
申请日：2005-03-15
申请人： Cheng Horng , Ru-Ying Tong , Mao-Min Chen , Liubo Hong , Min Li
发明人： Cheng Horng , Ru-Ying Tong , Mao-Min Chen , Liubo Hong , Min Li
IPC分类号： H01L21/336
CPC分类号： H01L43/12
摘要： A method of forming a high performance MTJ in an MRAM array is disclosed. A Ta/Ru capping layer in a bottom conductor is sputter etched to remove the Ru layer and form an amorphous Ta capping layer. A key feature is a subsequent surface treatment of the Ta capping layer in a transient vacuum chamber where a self-annealing occurs and a surfactant layer is formed on the Ta surface. The resulting smooth and flat Ta surface promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-μm2.
摘要翻译：公开了一种在MRAM阵列中形成高性能MTJ的方法。溅射蚀刻底部导体中的Ta / Ru覆盖层以去除Ru层并形成无定形Ta覆盖层。一个关键的特征是在瞬态真空室中Ta覆盖层的后续表面处理，其中发生自退火并且在Ta表面上形成表面活性剂层。所得到的平滑且平坦的Ta表面促进在表面活性剂层上随后形成的MTJ层中的光滑和平坦的表面。对于0.3×0.6微米的MTJ位尺寸，35至40埃厚的NiFe（18％）自由层，由9至10埃厚的Al层的ROX氧化产生的AlO x势垒层，以及Ru / Ta / 使用Ru覆盖层得到大于40％的dR / R和约4000欧姆 - 姆2的RA。

10. 发明申请

US20050254293A1 Novel structure/method to fabricate a high-performance magnetic tunneling junction MRAM 失效
标题翻译：制造高性能磁隧道结MRAM的新型结构/方法
公开(公告)号：US20050254293A1
公开(公告)日：2005-11-17
申请号：US10844171
申请日：2004-05-12
申请人： Cheng Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
发明人： Cheng Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
IPC分类号： G11C11/00 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L43/08 , Y10S977/934 , Y10S977/935
摘要： An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.
摘要翻译：在由溅射蚀刻的Ta层覆盖的导电引线和磁保持层上形成MTJ（磁性隧道结）MRAM（磁性随机存取存储器）单元。作为溅射蚀刻的结果，Ta层具有光滑的表面，并且光滑的表面促进随后形成具有光滑的平坦层和自由基氧化（ROX）Al隧穿势垒层的下电极（钉扎/钉扎层），其中具有超薄，光滑，且具有较高的击穿电压。在Ta的溅射蚀刻层上形成NiCr种子层。在其开关特性，GMR比和结电阻方面，所得到的器件通常具有改进的性能特性。

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