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1. 发明授权

US07112528B2 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 失效
公开(公告)号：US07112528B2
公开(公告)日：2006-09-26
申请号：US10367214
申请日：2003-02-13
申请人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosley , Fusen Chen
发明人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosley , Fusen Chen
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L21/28562 , H01L21/76879
摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

2. 发明授权

US06537905B1 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 失效
标题翻译：使用铜线互连和选择性CVD铝插头的全平面化双镶嵌金属化
公开(公告)号：US06537905B1
公开(公告)日：2003-03-25
申请号：US08778205
申请日：1996-12-30
申请人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosley , Fusen Chen
发明人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosley , Fusen Chen
IPC分类号： H01L214763
CPC分类号： H01L21/28562 , H01L21/76879
摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
摘要翻译：本发明通常提供用于形成高度集成的互连件的金属化工艺。更具体地，本发明提供了一种双镶嵌互连模块，其通过填充形成在阻挡层内的金属线，优选铜，并入选择性化学气相沉积铝（CVD Al）。本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点，并减少了实现这种集成的流程步骤。

3. 发明授权

US06743714B2 Low temperature integrated metallization process and apparatus 失效
公开(公告)号：US06743714B2
公开(公告)日：2004-06-01
申请号：US10074938
申请日：2002-02-11
申请人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo , Liang-Yuh Chen
发明人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo , Liang-Yuh Chen
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

4. 发明授权

US6139697A Low temperature integrated via and trench fill process and apparatus 失效
标题翻译：低温集成通孔和沟槽填充工艺和设备
公开(公告)号：US6139697A
公开(公告)日：2000-10-31
申请号：US792292
申请日：1997-01-31
申请人： Liang-Yuh Chen , Roderick Craig Mosely , Fusen Chen , Rong Tao , Ted Guo
发明人： Liang-Yuh Chen , Roderick Craig Mosely , Fusen Chen , Rong Tao , Ted Guo
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , C23C14/34
CPC分类号： H01L21/76877
摘要： The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.
摘要翻译：本发明一般涉及在衬底上提供完整的通孔填充物和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。然后将CVD金属层（例如CVD Al或CVD Cu）在低温下沉积到耐火层上，以提供用于PVD Cu的保形润湿层。接下来，在低于金属的熔点温度的温度下，将PVD Cu沉积在先前形成的CVD Cu层上。所得到的CVD / PVD Cu层基本上无空隙。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Cu层。本发明的通孔填充方法也可以在CVD Cu和PVD Cu步骤之间的空气曝光成功。

5. 发明授权

US06605531B1 Hole-filling technique using CVD aluminum and PVD aluminum integration 失效
标题翻译：使用CVD铝和PVD铝整合的填孔技术
公开(公告)号：US06605531B1
公开(公告)日：2003-08-12
申请号：US09127010
申请日：1998-07-31
申请人： Ted Guo , Wei Shi , Liang-Yuh Chen
发明人： Ted Guo , Wei Shi , Liang-Yuh Chen
IPC分类号： H01L214763
CPC分类号： H01L21/2855 , H01L21/28556 , H01L21/76882
摘要： The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.
摘要翻译：本发明提供了一种通过在基板上沉积不足厚度的金属膜来填充基板上的孔的方法，以填充次半微米孔径，然后在低压室内在低于熔点的温度下将基板退火沉积金属膜。本发明还提供了通过在退火膜上物理气相沉积金属膜而在无空隙孔上形成平坦化膜。

6. 发明授权

US06169030A Metallization process and method 失效
标题翻译：金属化过程和方法
公开(公告)号：US06169030A
公开(公告)日：2001-01-02
申请号：US09007233
申请日：1998-01-14
申请人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
发明人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
IPC分类号： H01L2144
CPC分类号： C23C14/32 , C23C14/025 , C23C14/046 , H01L21/2855 , H01L21/76877
摘要： The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power. Even more preferably, the plasma power is varied from a first discrete low plasma power to a second discrete low plasma power to a third discrete high plasma power.
摘要翻译：本发明通常提供了一种改进的方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在高纵横比，半微米应用中形成连续的无空隙互连。本发明提供了一种多步骤PVD工艺，其中等离子体功率对于每个步骤而言是变化的，以获得良好的填充特性以及良好的反射率，形态和产量。初始等离子体功率相对较低，以确保孔的良好的无空隙填充，然后增加等离子体功率以获得期望的反射率和形态特征。本发明提供一种孔填充方法，其包括在物理气相沉积中物理气相沉积衬底上的金属并改变等离子体功率。优选地，等离子体功率从第一离散低等离子体功率变化到第二离散高等离子体功率。更优选地，等离子体功率从第一离散低等离子体功率变化到第二离散低等离子体功率到第三离散高等离子体功率。

7. 发明授权

US6110828A In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization 失效
标题翻译：使用选择性CVD AL进行集成插头/互连金属化的现场封盖铝插头（CAP）工艺
公开(公告)号：US6110828A
公开(公告)日：2000-08-29
申请号：US791653
申请日：1996-12-30
申请人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan
发明人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/443
CPC分类号： H01L21/76879
摘要： The present invention generally provides a method of forming a structure having a selective CVD metal plug with a continuous barrier layer formed thereon. More particularly, the present invention applies a thin layer of warm PVD metal over a selective CVD metal plug and adjacent nodules on the dielectric field to planarize the metal surface. A barrier is then deposited over the planarized metal surface. Therefore, the invention provides the advantages of having (1) void-free, sub-half micron selective CVD metal via plugs and interconnects, and (2) a reduced number of process steps without the use of CMP, and (3) barrier layers over the metal plugs to improve the electromigration resistance of the metal.
摘要翻译：本发明通常提供一种形成具有在其上形成有连续势垒层的选择性CVD金属塞的结构的方法。更具体地说，本发明在选择性CVD金属塞上和在电介质场上的相邻结节上施加薄层的温热PVD金属以使金属表面平坦化。然后在平坦化的金属表面上沉积屏障。因此，本发明提供了具有（1）无空隙的半微米选择性CVD金属通孔塞和互连件的优点，和（2）减少数量的工艺步骤而不使用CMP，以及（3）阻挡层在金属插头上提高金属的电迁移阻力。

8. 发明授权

US06518176B2 Method of selective formation of a barrier layer for a contact level via 失效
标题翻译：选择性形成接触层通孔阻挡层的方法
公开(公告)号：US06518176B2
公开(公告)日：2003-02-11
申请号：US09092747
申请日：1998-06-05
申请人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan , Roderick C. Mosely
发明人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan , Roderick C. Mosely
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A contact level via and a method of performing selective deposition of a barrier layer to form a contact level via for selective aluminum metallization. Specifically, the method forms a self-aligned silicide region by depositing titanium atop a structure containing a contact level via, converting the titanium in the contact regions into titanium silicide, removing the unreacted titanium, and performing nitridation of the titanium silicide to complete a barrier layer located in only the contact region of the via. Once the barrier layer is formed, the layer can be optionally fortified through oxygen stuffing to create an effective barrier layer for aluminum metallization.
摘要翻译：接触电平通孔和执行选择性沉积阻挡层以形成用于选择性铝金属化的接触电平通路的方法。具体地，该方法通过在包含接触电平通孔的结构上方沉积钛而形成自对准硅化物区域，将接触区域中的钛转化为硅化钛，除去未反应的钛，并进行硅化钛的氮化以完成阻挡层层位于通孔的接触区域中。一旦形成了阻挡层，就可以通过氧气填充来选择性地强化该层，以产生用于铝金属化的有效阻挡层。

9. 发明授权

US06509274B1 Method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate 失效
标题翻译：在半导体衬底中的铝填充通孔上形成铝线的方法
公开(公告)号：US06509274B1
公开(公告)日：2003-01-21
申请号：US09632486
申请日：2000-08-04
申请人： Ted Guo , Jing-Pei Chou , Liang-Yuh Chen , Roderick C. Mosely
发明人： Ted Guo , Jing-Pei Chou , Liang-Yuh Chen , Roderick C. Mosely
IPC分类号： H01L21302
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76882
摘要： A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.
摘要翻译：一种用于在半导体衬底中的铝填充通孔上形成铝线的方法，其可以补偿所填充的通孔和线之间的一些不对准。通过在衬底上交替沉积衬垫阻挡层和铝层，可以使用不同的蚀刻化学性质，其可以各向异性地蚀刻用于形成线的铝层，而不会在铝填充的通孔中蚀刻空隙。

10. 发明授权

US06430458B1 Semi-selective chemical vapor deposition 失效
标题翻译：半选择性化学气相沉积
公开(公告)号：US06430458B1
公开(公告)日：2002-08-06
申请号：US09371617
申请日：1999-08-10
申请人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
发明人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
IPC分类号： B05D114
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The present invention is an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.
摘要翻译：本发明是一种用于通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的装置和方法。绝缘层优先沉积在衬底的场上以延迟或抑制场上金属的成核。然后将CVD金属沉积到衬底上并选择性地生长在接触孔中，或通过其中阻挡层用作成核层。该方法优选在包括PVD和CVD处理室的多室系统中进行，使得一旦将基底引入真空环境中，接触孔和通孔的填充发生，而在图案上没有形成氧化物层基质。

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