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1. 发明授权

US06518176B2 Method of selective formation of a barrier layer for a contact level via 失效
标题翻译：选择性形成接触层通孔阻挡层的方法
公开(公告)号：US06518176B2
公开(公告)日：2003-02-11
申请号：US09092747
申请日：1998-06-05
申请人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan , Roderick C. Mosely
发明人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan , Roderick C. Mosely
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A contact level via and a method of performing selective deposition of a barrier layer to form a contact level via for selective aluminum metallization. Specifically, the method forms a self-aligned silicide region by depositing titanium atop a structure containing a contact level via, converting the titanium in the contact regions into titanium silicide, removing the unreacted titanium, and performing nitridation of the titanium silicide to complete a barrier layer located in only the contact region of the via. Once the barrier layer is formed, the layer can be optionally fortified through oxygen stuffing to create an effective barrier layer for aluminum metallization.
摘要翻译：接触电平通孔和执行选择性沉积阻挡层以形成用于选择性铝金属化的接触电平通路的方法。具体地，该方法通过在包含接触电平通孔的结构上方沉积钛而形成自对准硅化物区域，将接触区域中的钛转化为硅化钛，除去未反应的钛，并进行硅化钛的氮化以完成阻挡层层位于通孔的接触区域中。一旦形成了阻挡层，就可以通过氧气填充来选择性地强化该层，以产生用于铝金属化的有效阻挡层。

2. 发明授权

US6110828A In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization 失效
标题翻译：使用选择性CVD AL进行集成插头/互连金属化的现场封盖铝插头（CAP）工艺
公开(公告)号：US6110828A
公开(公告)日：2000-08-29
申请号：US791653
申请日：1996-12-30
申请人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan
发明人： Ted Guo , Liang-Yuh Chen , Suchitra Subrahmanyan
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/443
CPC分类号： H01L21/76879
摘要： The present invention generally provides a method of forming a structure having a selective CVD metal plug with a continuous barrier layer formed thereon. More particularly, the present invention applies a thin layer of warm PVD metal over a selective CVD metal plug and adjacent nodules on the dielectric field to planarize the metal surface. A barrier is then deposited over the planarized metal surface. Therefore, the invention provides the advantages of having (1) void-free, sub-half micron selective CVD metal via plugs and interconnects, and (2) a reduced number of process steps without the use of CMP, and (3) barrier layers over the metal plugs to improve the electromigration resistance of the metal.
摘要翻译：本发明通常提供一种形成具有在其上形成有连续势垒层的选择性CVD金属塞的结构的方法。更具体地说，本发明在选择性CVD金属塞上和在电介质场上的相邻结节上施加薄层的温热PVD金属以使金属表面平坦化。然后在平坦化的金属表面上沉积屏障。因此，本发明提供了具有（1）无空隙的半微米选择性CVD金属通孔塞和互连件的优点，和（2）减少数量的工艺步骤而不使用CMP，以及（3）阻挡层在金属插头上提高金属的电迁移阻力。

3. 发明授权

US06509274B1 Method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate 失效
标题翻译：在半导体衬底中的铝填充通孔上形成铝线的方法
公开(公告)号：US06509274B1
公开(公告)日：2003-01-21
申请号：US09632486
申请日：2000-08-04
申请人： Ted Guo , Jing-Pei Chou , Liang-Yuh Chen , Roderick C. Mosely
发明人： Ted Guo , Jing-Pei Chou , Liang-Yuh Chen , Roderick C. Mosely
IPC分类号： H01L21302
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76882
摘要： A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.
摘要翻译：一种用于在半导体衬底中的铝填充通孔上形成铝线的方法，其可以补偿所填充的通孔和线之间的一些不对准。通过在衬底上交替沉积衬垫阻挡层和铝层，可以使用不同的蚀刻化学性质，其可以各向异性地蚀刻用于形成线的铝层，而不会在铝填充的通孔中蚀刻空隙。

4. 发明授权

US6077781A Single step process for blanket-selective CVD aluminum deposition 失效
标题翻译：毯式选择性CVD铝沉积的单步法
公开(公告)号：US6077781A
公开(公告)日：2000-06-20
申请号：US620405
申请日：1996-03-22
申请人： Ted Guo , Liang-Yuh Chen , Mehul Naik , Roderick C. Mosely
发明人： Ted Guo , Liang-Yuh Chen , Mehul Naik , Roderick C. Mosely
IPC分类号： H01L21/285 , C23C14/56 , C23C16/54 , H01L21/28 , H01L21/3205 , H01L21/677 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectric layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.
摘要翻译：本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。在本发明的一个方面中，在导电部件上形成电介质层。然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以露出孔底板上的下面的导电构件。然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间层。

5. 发明授权

US06458684B1 Single step process for blanket-selective CVD aluminum deposition 失效
标题翻译：毯式选择性CVD铝沉积的单步法
公开(公告)号：US06458684B1
公开(公告)日：2002-10-01
申请号：US09497390
申请日：2000-02-03
申请人： Ted Guo , Liang-Yuh Chen , Mehul Naik , Roderick C. Mosely
发明人： Ted Guo , Liang-Yuh Chen , Mehul Naik , Roderick C. Mosely
IPC分类号： H01L2144
CPC分类号： C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.
摘要翻译：本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。在本发明的一个方面中，在导电部件上形成电介质层。然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以暴露孔底板上的下面的导电构件。然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间层。

6. 发明授权

US06693030B1 Reactive preclean prior to metallization for sub-quarter micron application 失效
标题翻译：金属化之前的反应性预清洗用于二分之一微米的应用
公开(公告)号：US06693030B1
公开(公告)日：2004-02-17
申请号：US09617522
申请日：2000-07-14
申请人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
发明人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
IPC分类号： H01L214763
CPC分类号： C23C16/0236 , C23C14/022 , H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76861 , Y10S438/906
摘要： The present invention generally provides a precleaning process prior to moralization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available moralization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and moralization steps can be conducted on available integrated processing platforms.
摘要翻译：本发明通常提供在衬底上的亚微米特征的道德化之前的预清洗过程。该方法包括用来自诸如氧的反应性气体的等离子体，CF 4 / O 2或He / NF 3的混合物的混合物的自由基清洗亚微米特征，其中等离子体优选由远程等离子体源产生，并且基团是输送到其中设置基板的室。残留在亚微米特征中的天然氧化物优选通过用含有氢的等离子体进行处理而在第二步骤中还原。在第一个或两个预清洗步骤之后，特征可以通过可用的道德化技术用金属填充，其通常包括在沉积铝，铜或钨之前在暴露的电介质表面上沉积阻挡层/衬垫层。预处理和道德化步骤可以在现有的综合处理平台上进行。

7. 发明授权

US06905965B2 Reactive preclean prior to metallization for sub-quarter micron application 失效
标题翻译：金属化之前的反应性预清洗用于二分之一微米的应用
公开(公告)号：US06905965B2
公开(公告)日：2005-06-14
申请号：US10780105
申请日：2004-02-17
申请人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
发明人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
IPC分类号： C23C14/02 , C23C16/02 , H01L21/285 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/768 , H01L21/44
CPC分类号： C23C16/0236 , C23C14/022 , H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76861 , Y10S438/906
摘要： The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.
摘要翻译：本发明通常在金属化之前提供在衬底上的亚微米特征的预清洗工艺。该方法包括用来自反应气体的等离子体（例如氧气），CF 3/4 O 2 / O 2混合物或He / NF混合物的自由基清洗亚微米特征其中等离子体优选地由远程等离子体源产生，并且自由基被输送到其中设置衬底的室。残留在亚微米特征中的天然氧化物优选通过用含有氢的等离子体进行处理而在第二步骤中还原。在第一或两个预清洗步骤之后，特征可以通过可用的金属化技术用金属填充，其通常包括在沉积铝，铜或钨之前在暴露的电介质表面上沉积阻挡层/衬垫层。预清洗和金属化步骤可以在可用的集成处理平台上进行。

8. 发明授权

US6107192A Reactive preclean prior to metallization for sub-quarter micron application 失效
标题翻译：金属化之前的反应性预清洗用于二分之一微米的应用
公开(公告)号：US6107192A
公开(公告)日：2000-08-22
申请号：US746
申请日：1997-12-30
申请人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
发明人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
IPC分类号： C23C14/02 , C23C16/02 , H01L21/285 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/768 , H01L21/4763
CPC分类号： C23C16/0236 , C23C14/022 , H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76861 , Y10S438/906
摘要： The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF.sub.4 /O.sub.2, or a mixture of He/NF.sub.3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.
摘要翻译：本发明通常在金属化之前提供在衬底上的亚微米特征的预清洗工艺。该方法包括用来自诸如氧的反应性气体的等离子体，CF 4 / O 2或He / NF 3的混合物的混合物的自由基清洗亚微米特征，其中等离子体优选由远程等离子体源产生，并且基团是输送到其中设置基板的室。残留在亚微米特征中的天然氧化物优选通过用含有氢的等离子体进行处理而在第二步骤中还原。在第一或两个预清洗步骤之后，特征可以通过可用的金属化技术用金属填充，其通常包括在沉积铝，铜或钨之前在暴露的电介质表面上沉积阻挡层/衬垫层。预清洗和金属化步骤可以在可用的集成处理平台上进行。

9. 发明授权

US06743714B2 Low temperature integrated metallization process and apparatus 失效
公开(公告)号：US06743714B2
公开(公告)日：2004-06-01
申请号：US10074938
申请日：2002-02-11
申请人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo , Liang-Yuh Chen
发明人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo , Liang-Yuh Chen
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

10. 发明授权

US6080665A Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum 失效
标题翻译：集成的氮处理钛层，以防止钛和铝的相互作用
公开(公告)号：US6080665A
公开(公告)日：2000-06-27
申请号：US840209
申请日：1997-04-11
申请人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosely
IPC分类号： H01L21/28 , C23C14/14 , C23C14/58 , C23C16/06 , C23C16/56 , H01L21/203 , H01L21/3205 , H01L21/768 , H01L21/44
CPC分类号： C23C14/5826 , C23C14/14 , C23C14/586 , C23C16/06 , C23C16/56 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877
摘要： The present invention generally provides a method for processing a substrate having exposed surfaces of titanium and/or silicon prior to deposition of aluminum. The substrate is positioned adjacent a process zone which provides a nitrogen plasma so that exposed areas of titanium and silicon on the substrate are stuffed with nitrogen to form titanium nitride (TiN) and various compounds of silicon and nitrogen (Si.sub.x N.sub.y), respectively. The nitrogen treated surfaces, i.e, TiN and silicon/nitrogen compounds, are resistant to interaction with aluminum. In this manner, the formation of electrically insulating TiAl.sub.3 and/or the spiking of silicon is reduced or eliminated.
摘要翻译：本发明通常提供一种在沉积铝之前处理具有钛和/或硅的暴露表面的衬底的方法。衬底位于提供氮等离子体的工艺区域附近，使得衬底上的钛和硅的暴露区域填充氮气，以分别形成氮化钛（TiN）和各种硅和氮化合物（SixNy）。氮处理的表面即TiN和硅/氮化合物对铝的相互作用具有抗性。以这种方式，减少或消除了电绝缘TiAl 3的形成和/或硅的尖峰。

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