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1. 发明申请

US20100013681A1 Preprocessing Variable-Length Code (VLC) Bitstream Information 有权
标题翻译：预处理可变长度码（VLC）比特流信息
公开(公告)号：US20100013681A1
公开(公告)日：2010-01-21
申请号：US12173204
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/40
摘要： An information handling system includes a processor that may perform preprocessing on a variable-length code (VLC) bitstream before decoding the bitstream. The bitstream includes multiple codewords. The processor analyzes incoming VLC bitstream information and generates codeword table information for storage in a system memory or a VLC codeword tables location. The processor generates a VLC lookup table from the information in the VLC codeword tables and stores that VLC lookup table in a system memory of the IHS. The VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在对位流进行解码之前对可变长度码（VLC）比特流执行预处理。比特流包括多个码字。处理器分析传入的VLC比特流信息，并生成用于存储在系统存储器或VLC码字表位置中的码字表信息。处理器从VLC码字表中的信息生成VLC查找表，并将该VLC查找表存储在IHS的系统存储器中。 VLC查找表可以通过引导零计数和位长度的可能性来呈现二维索引。

2. 发明授权

US07791509B2 Preprocessing variable-length code (VLC) bitstream information 有权
标题翻译：预处理可变长度码（VLC）比特流信息
公开(公告)号：US07791509B2
公开(公告)日：2010-09-07
申请号：US12173204
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/40
摘要： An information handling system includes a processor that may perform preprocessing on a variable-length code (VLC) bitstream before decoding the bitstream. The bitstream includes multiple codewords. The processor analyzes incoming VLC bitstream information and generates codeword table information for storage in a system memory or a VLC codeword tables location. The processor generates a VLC lookup table from the information in the VLC codeword tables and stores that VLC lookup table in a system memory of the IHS. The VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在对位流进行解码之前对可变长度码（VLC）比特流执行预处理。比特流包括多个码字。处理器分析传入的VLC比特流信息，并生成用于存储在系统存储器或VLC码字表位置中的码字表信息。处理器从VLC码字表中的信息生成VLC查找表，并将该VLC查找表存储在IHS的系统存储器中。 VLC查找表可以通过引导零计数和位长度的可能性来呈现二维索引。

3. 发明授权

US07777653B2 Decoding variable-length code (VLC) bitstream information 有权
标题翻译：解码可变长度码（VLC）比特流信息
公开(公告)号：US07777653B2
公开(公告)日：2010-08-17
申请号：US12173192
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： An information handling system includes a processor that may perform decoding of a variable-length code (VLC) bitstream after preprocessing the bitstream. The bitstream includes multiple VLC symbols as binary codewords. The processor analyzes incoming VLC bitstream information and generates VLC codeword symbol information in conformance with a VLC lookup table. The processor may access a 2 dimensional VLC lookup table in real time or on-the-fly. The VLC lookup table may reside in a system memory of the IHS. The single VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在预处理比特流之后执行可变长度码（VLC）比特流的解码。比特流包括多个VLC符号作为二进制码字。处理器分析传入的VLC比特流信息，并根据VLC查找表生成VLC码字符号信息。处理器可以实时或即时访问二维VLC查找表。 VLC查找表可以驻留在IHS的系统存储器中。单个VLC查找表可以通过引导零计数和位长度可能性来展现二维索引。

4. 发明申请

US20100013680A1 Decoding Variable-Length Code (VLC) Bitstream Information 有权
标题翻译：解码可变长度码（VLC）比特流信息
公开(公告)号：US20100013680A1
公开(公告)日：2010-01-21
申请号：US12173192
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： An information handling system includes a processor that may perform decoding of a variable-length code (VLC) bitstream after preprocessing the bitstream. The bitstream includes multiple VLC symbols as binary codewords. The processor analyzes incoming VLC bitstream information and generates VLC codeword symbol information in conformance with a VLC lookup table. The processor may access a 2 dimensional VLC lookup table in real time or on-the-fly. The VLC lookup table may reside in a system memory of the IHS. The single VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在预处理比特流之后执行可变长度码（VLC）比特流的解码。比特流包括多个VLC符号作为二进制码字。处理器分析传入的VLC比特流信息，并根据VLC查找表生成VLC码字符号信息。处理器可以实时或即时访问二维VLC查找表。 VLC查找表可以驻留在IHS的系统存储器中。单个VLC查找表可以通过引导零计数和位长度可能性来展现二维索引。

5. 发明授权

US08140585B2 Method and apparatus for partitioning and sorting a data set on a multi-processor system 失效
标题翻译：用于对多处理器系统上的数据集进行分区和排序的方法和装置
公开(公告)号：US08140585B2
公开(公告)日：2012-03-20
申请号：US12508628
申请日：2009-07-24
申请人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
发明人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
IPC分类号： G06F17/30
CPC分类号： G06F9/3891 , G06F7/36 , G06F9/30021 , G06F9/5066
摘要： The present invention provides a method and apparatus for partitioning, sorting a data set on a multi-processor system. Herein, the multi-processor system has at least one core processor and a plurality of accelerators. The method for partitioning a data set comprises: partitioning iteratively said data set into a plurality of buckets corresponding to different data ranges by using said plurality of accelerators in parallel, wherein each of the plurality of buckets could be stored in local storage of said plurality of accelerators; wherein in each iteration, the method comprises: roughly partitioning said data set into a plurality of large buckets; obtaining parameters of said data set that can indicate the distribution of data values in that data set; determining a plurality of data ranges for said data set based on said parameters; and partitioning said plurality of large buckets into a plurality of small buckets corresponding to the plurality of data ranges respectively by using said plurality of accelerators in parallel, wherein each of said plurality of accelerators, for each element in the large bucket it is partitioning, determines a data range to which that element belongs among the plurality of data ranges by computation.
摘要翻译：本发明提供了一种用于对多处理器系统上的数据集进行分区，排序的方法和装置。这里，多处理器系统具有至少一个核心处理器和多个加速器。用于分割数据集的方法包括：通过并行地使用所述多个加速器将所述数据集迭代地分割成对应于不同数据范围的多个存储桶，其中所述多个存储桶中的每一个可被存储在所述多个加速器其中在每次迭代中，所述方法包括：将所述数据集大致划分成多个大桶; 获取可以指示该数据集中的数据值的分布的所述数据集的参数; 基于所述参数确定所述数据集的多个数据范围; 并且通过并行地使用所述多个加速器，将所述多个大存储桶分别分别对应于所述多个数据范围的多个小桶，其中，所述多个加速器中的每一个对于大桶中的每个元件进行分区，确定通过计算，该元素属于多个数据范围中的数据范围。

6. 发明申请

US20100031003A1 METHOD AND APPARATUS FOR PARTITIONING AND SORTING A DATA SET ON A MULTI-PROCESSOR SYSTEM 失效
标题翻译：用于在多处理器系统上分配和分配数据集的方法和装置
公开(公告)号：US20100031003A1
公开(公告)日：2010-02-04
申请号：US12508628
申请日：2009-07-24
申请人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
发明人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
IPC分类号： G06F15/76 , G06F17/00 , G06F9/06
CPC分类号： G06F9/3891 , G06F7/36 , G06F9/30021 , G06F9/5066
摘要： The present invention provides a method and apparatus for partitioning, sorting a data set on a multi-processor system. Herein, the multi-processor system has at least one core processor and a plurality of accelerators. The method for partitioning a data set comprises: partitioning iteratively said data set into a plurality of buckets corresponding to different data ranges by using said plurality of accelerators in parallel, wherein each of the plurality of buckets could be stored in local storage of said plurality of accelerators; wherein in each iteration, the method comprises: roughly partitioning said data set into a plurality of large buckets; obtaining parameters of said data set that can indicate the distribution of data values in that data set; determining a plurality of data ranges for said data set based on said parameters; and partitioning said plurality of large buckets into a plurality of small buckets corresponding to the plurality of data ranges respectively by using said plurality of accelerators in parallel, wherein each of said plurality of accelerators, for each element in the large bucket it is partitioning, determines a data range to which that element belongs among the plurality of data ranges by computation.
摘要翻译：本发明提供了一种用于对多处理器系统上的数据集进行分区，排序的方法和装置。这里，多处理器系统具有至少一个核心处理器和多个加速器。用于分割数据集的方法包括：通过并行地使用所述多个加速器将所述数据集迭代地分割成对应于不同数据范围的多个存储桶，其中所述多个存储桶中的每一个可被存储在所述多个加速器其中在每次迭代中，所述方法包括：将所述数据集大致划分成多个大桶; 获取可以指示该数据集中的数据值的分布的所述数据集的参数; 基于所述参数确定所述数据集的多个数据范围; 并且通过并行地使用所述多个加速器，将所述多个大存储桶分别分别对应于所述多个数据范围的多个小桶，其中，所述多个加速器中的每一个对于大桶中的每个元件进行分区，确定通过计算，该元素属于多个数据范围中的数据范围。

7. 发明申请

US20090089507A1 OVERLAY INSTRUCTION ACCESSING UNIT AND OVERLAY INSTRUCTION ACCESSING METHOD 有权
标题翻译：覆盖指导访问单位和覆盖指导访问方法
公开(公告)号：US20090089507A1
公开(公告)日：2009-04-02
申请号：US12239070
申请日：2008-09-26
申请人： Liang Chen , Kuan Feng , Wang Zheng , Min Zhu
发明人： Liang Chen , Kuan Feng , Wang Zheng , Min Zhu
IPC分类号： G06F9/45 , G06F12/00
CPC分类号： G06F9/3802 , G06F8/433 , G06F9/3017 , G06F9/30178 , G06F9/382 , G06F9/3846 , G06F9/3885 , G06F9/3891
摘要： The present invention provides an overlay instruction accessing unit and method, and a method and apparatus for compressing and storing a program. The overlay instruction accessing unit is used to execute a program stored in a memory in the form of a plurality of compressed program segments, and compresses: a buffer; a processing unit for issuing an instruction reading request, reading an instruction from the buffer, and executing the instruction; and a decompressing unit for reading a requested compressed instruction segment from the memory in response to the instruction reading request of the processing unit, decompressing the compressed instruction segment, and storing the decompressed instruction segment in the buffer, wherein while the processing unit is executing the instruction segment, the decompressing unit reads, according to a storage address of a compressed program segment to be invoked in a header corresponding to the instruction segment, a corresponding compressed instruction segment from the memory, decompresses the compressed instruction segment, and stores the decompressed instruction segment in the buffer for later use by the processing unit.
摘要翻译：本发明提供一种覆盖指令访问单元和方法，以及用于压缩和存储程序的方法和装置。覆盖指令访问单元用于以多个压缩程序段的形式执行存储在存储器中的程序，并且压缩：缓冲器; 处理单元，用于发出指令读取请求，从缓冲器读取指令并执行指令; 以及解压缩单元，用于响应于处理单元的指令读取请求从存储器读取所请求的压缩指令段，解压缩压缩指令段，并将解压缩的指令段存储在缓冲器中，其中当处理单元正在执行时指令段，解压缩单元根据在与指令段对应的报头中要调用的压缩程序段的存储地址读取来自存储器的对应的压缩指令段，解压缩压缩指令段，并存储解压缩指令缓冲区中的段，以供稍后由处理单元使用。

8. 发明授权

US08255592B2 Managing data movement in a cell broadband engine processor 失效
标题翻译：管理单元宽带引擎处理器中的数据移动
公开(公告)号：US08255592B2
公开(公告)日：2012-08-28
申请号：US12238073
申请日：2008-09-25
申请人： Zheng Wang , Liang Chen , Wenjun Wang , Kuan Feng
发明人： Zheng Wang , Liang Chen , Wenjun Wang , Kuan Feng
IPC分类号： G06F13/28 , G06F9/46
CPC分类号： G06F15/16
摘要： A cell broadband engine processor includes a memory a power processing element (PPE) coupled with the memory, and a plurality of synergistic processing elements. The PPE creates a SPE as a computing SPE for an application. The PPE determines idles ones of the plurality of SPEs, and creates an idle one of the plurality SPEs as a managing SPE. Each of the plurality of SPEs is associated with a local storage. The managing SPE informs the computing SPE of a starting effective address of the local storage of the managing SPE and an effective address for a command queue. The managing SPE manages movement of data associated with computing of the computing SPE based on one or more commands associated with the application. A computing SPE sends the one or more commands to the managing SPE for insertion into the command queue.
摘要翻译：小区宽带引擎处理器包括与存储器耦合的功率处理元件（PPE）和多个协同处理元件的存储器。 PPE创建一个SPE作为应用程序的计算SPE。 PPE确定多个SPE中的空闲数据，并且创建多个SPE中的空闲的一个作为管理SPE。多个SPE中的每一个与本地存储器相关联。管理SPE将计算SPE通知管理SPE的本地存储的起始有效地址和命令队列的有效地址。管理SPE基于与应用相关联的一个或多个命令来管理与计算SPE的计算相关联的数据的移动。计算SPE将一个或多个命令发送到管理SPE以插入到命令队列中。

9. 发明申请

US20090089559A1 METHOD OF MANAGING DATA MOVEMENT AND CELL BROADBAND ENGINE PROCESSOR USING THE SAME 失效
标题翻译：管理数据运动的方法和使用该数据运动的小区宽带发动机处理器
公开(公告)号：US20090089559A1
公开(公告)日：2009-04-02
申请号：US12238073
申请日：2008-09-25
申请人： Zheng Wang , Liang Chen , Wenjun Wang , Kuan Feng
发明人： Zheng Wang , Liang Chen , Wenjun Wang , Kuan Feng
IPC分类号： G06F9/06
CPC分类号： G06F15/16
摘要： A method of managing data movement in a cell broadband engine processor, comprising: determining one or more idle synergistic processing elements among multiple SPEs in the cell broadband engine processor as a managing SPE, and informing a computing SPE among said multiple SPEs of a starting effective address of a LS of said managing SPE and an effective address for a command queue; and said managing SPE managing movement of data associated with computing of said computing SPE based on the command queue from the computing SPE.
摘要翻译：一种管理小区宽带引擎处理器中的数据移动的方法，包括：将所述小区宽带引擎处理器中的多个SPE中的一个或多个空闲协同处理元件确定为管理SPE，以及将所述多个SPE中的计算SPE通知起始有效所述管理SPE的LS的地址和命令队列的有效地址; 并且管理SPE基于来自计算SPE的命令队列来管理与所述计算SPE的计算相关联的数据的移动。

10. 发明授权

US08286151B2 Overlay instruction accessing unit and overlay instruction accessing method 有权
标题翻译：覆盖指令访问单元和覆盖指令访问方法
公开(公告)号：US08286151B2
公开(公告)日：2012-10-09
申请号：US12239070
申请日：2008-09-26
申请人： Liang Chen , Kuan Feng , Wang Zheng , Min Zhu
发明人： Liang Chen , Kuan Feng , Wang Zheng , Min Zhu
IPC分类号： G06F3/45 , G00F15/00
CPC分类号： G06F9/3802 , G06F8/433 , G06F9/3017 , G06F9/30178 , G06F9/382 , G06F9/3846 , G06F9/3885 , G06F9/3891
摘要： The present invention provides an overlay instruction accessing unit and method, and a method and apparatus for compressing and storing a program. The overlay instruction accessing unit is used to execute a program stored in a memory in the form of a plurality of compressed program segments, and compresses: a buffer; a processing unit for issuing an instruction reading request, reading an instruction from the buffer, and executing the instruction; and a decompressing unit for reading a requested compressed instruction segment from the memory in response to the instruction reading request of the processing unit, decompressing the compressed instruction segment, and storing the decompressed instruction segment in the buffer, wherein while the processing unit is executing the instruction segment, the decompressing unit reads, according to a storage address of a compressed program segment to be invoked in a header corresponding to the instruction segment, a corresponding compressed instruction segment from the memory, decompresses the compressed instruction segment, and stores the decompressed instruction segment in the buffer for later use by the processing unit.
摘要翻译：本发明提供一种覆盖指令访问单元和方法，以及用于压缩和存储程序的方法和装置。覆盖指令访问单元用于以多个压缩程序段的形式执行存储在存储器中的程序，并且压缩：缓冲器; 处理单元，用于发出指令读取请求，从缓冲器读取指令并执行指令; 以及解压缩单元，用于响应于处理单元的指令读取请求从存储器读取所请求的压缩指令段，解压缩压缩指令段，并将解压缩的指令段存储在缓冲器中，其中当处理单元正在执行时指令段，解压缩单元根据在与指令段对应的报头中要调用的压缩程序段的存储地址读取来自存储器的对应的压缩指令段，解压缩压缩指令段，并存储解压缩指令缓冲区中的段，以供稍后由处理单元使用。

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