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1. 发明授权

US08140585B2 Method and apparatus for partitioning and sorting a data set on a multi-processor system 失效
标题翻译：用于对多处理器系统上的数据集进行分区和排序的方法和装置
公开(公告)号：US08140585B2
公开(公告)日：2012-03-20
申请号：US12508628
申请日：2009-07-24
申请人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
发明人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
IPC分类号： G06F17/30
CPC分类号： G06F9/3891 , G06F7/36 , G06F9/30021 , G06F9/5066
摘要： The present invention provides a method and apparatus for partitioning, sorting a data set on a multi-processor system. Herein, the multi-processor system has at least one core processor and a plurality of accelerators. The method for partitioning a data set comprises: partitioning iteratively said data set into a plurality of buckets corresponding to different data ranges by using said plurality of accelerators in parallel, wherein each of the plurality of buckets could be stored in local storage of said plurality of accelerators; wherein in each iteration, the method comprises: roughly partitioning said data set into a plurality of large buckets; obtaining parameters of said data set that can indicate the distribution of data values in that data set; determining a plurality of data ranges for said data set based on said parameters; and partitioning said plurality of large buckets into a plurality of small buckets corresponding to the plurality of data ranges respectively by using said plurality of accelerators in parallel, wherein each of said plurality of accelerators, for each element in the large bucket it is partitioning, determines a data range to which that element belongs among the plurality of data ranges by computation.
摘要翻译：本发明提供了一种用于对多处理器系统上的数据集进行分区，排序的方法和装置。这里，多处理器系统具有至少一个核心处理器和多个加速器。用于分割数据集的方法包括：通过并行地使用所述多个加速器将所述数据集迭代地分割成对应于不同数据范围的多个存储桶，其中所述多个存储桶中的每一个可被存储在所述多个加速器其中在每次迭代中，所述方法包括：将所述数据集大致划分成多个大桶; 获取可以指示该数据集中的数据值的分布的所述数据集的参数; 基于所述参数确定所述数据集的多个数据范围; 并且通过并行地使用所述多个加速器，将所述多个大存储桶分别分别对应于所述多个数据范围的多个小桶，其中，所述多个加速器中的每一个对于大桶中的每个元件进行分区，确定通过计算，该元素属于多个数据范围中的数据范围。

2. 发明申请

US20100031003A1 METHOD AND APPARATUS FOR PARTITIONING AND SORTING A DATA SET ON A MULTI-PROCESSOR SYSTEM 失效
标题翻译：用于在多处理器系统上分配和分配数据集的方法和装置
公开(公告)号：US20100031003A1
公开(公告)日：2010-02-04
申请号：US12508628
申请日：2009-07-24
申请人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
发明人： Liang Chen , Kuan Feng , Yonghua Lin , Sheng Xu
IPC分类号： G06F15/76 , G06F17/00 , G06F9/06
CPC分类号： G06F9/3891 , G06F7/36 , G06F9/30021 , G06F9/5066
摘要： The present invention provides a method and apparatus for partitioning, sorting a data set on a multi-processor system. Herein, the multi-processor system has at least one core processor and a plurality of accelerators. The method for partitioning a data set comprises: partitioning iteratively said data set into a plurality of buckets corresponding to different data ranges by using said plurality of accelerators in parallel, wherein each of the plurality of buckets could be stored in local storage of said plurality of accelerators; wherein in each iteration, the method comprises: roughly partitioning said data set into a plurality of large buckets; obtaining parameters of said data set that can indicate the distribution of data values in that data set; determining a plurality of data ranges for said data set based on said parameters; and partitioning said plurality of large buckets into a plurality of small buckets corresponding to the plurality of data ranges respectively by using said plurality of accelerators in parallel, wherein each of said plurality of accelerators, for each element in the large bucket it is partitioning, determines a data range to which that element belongs among the plurality of data ranges by computation.
摘要翻译：本发明提供了一种用于对多处理器系统上的数据集进行分区，排序的方法和装置。这里，多处理器系统具有至少一个核心处理器和多个加速器。用于分割数据集的方法包括：通过并行地使用所述多个加速器将所述数据集迭代地分割成对应于不同数据范围的多个存储桶，其中所述多个存储桶中的每一个可被存储在所述多个加速器其中在每次迭代中，所述方法包括：将所述数据集大致划分成多个大桶; 获取可以指示该数据集中的数据值的分布的所述数据集的参数; 基于所述参数确定所述数据集的多个数据范围; 并且通过并行地使用所述多个加速器，将所述多个大存储桶分别分别对应于所述多个数据范围的多个小桶，其中，所述多个加速器中的每一个对于大桶中的每个元件进行分区，确定通过计算，该元素属于多个数据范围中的数据范围。

3. 发明申请

US20100013681A1 Preprocessing Variable-Length Code (VLC) Bitstream Information 有权
标题翻译：预处理可变长度码（VLC）比特流信息
公开(公告)号：US20100013681A1
公开(公告)日：2010-01-21
申请号：US12173204
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/40
摘要： An information handling system includes a processor that may perform preprocessing on a variable-length code (VLC) bitstream before decoding the bitstream. The bitstream includes multiple codewords. The processor analyzes incoming VLC bitstream information and generates codeword table information for storage in a system memory or a VLC codeword tables location. The processor generates a VLC lookup table from the information in the VLC codeword tables and stores that VLC lookup table in a system memory of the IHS. The VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在对位流进行解码之前对可变长度码（VLC）比特流执行预处理。比特流包括多个码字。处理器分析传入的VLC比特流信息，并生成用于存储在系统存储器或VLC码字表位置中的码字表信息。处理器从VLC码字表中的信息生成VLC查找表，并将该VLC查找表存储在IHS的系统存储器中。 VLC查找表可以通过引导零计数和位长度的可能性来呈现二维索引。

4. 发明授权

US07791509B2 Preprocessing variable-length code (VLC) bitstream information 有权
标题翻译：预处理可变长度码（VLC）比特流信息
公开(公告)号：US07791509B2
公开(公告)日：2010-09-07
申请号：US12173204
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/40
摘要： An information handling system includes a processor that may perform preprocessing on a variable-length code (VLC) bitstream before decoding the bitstream. The bitstream includes multiple codewords. The processor analyzes incoming VLC bitstream information and generates codeword table information for storage in a system memory or a VLC codeword tables location. The processor generates a VLC lookup table from the information in the VLC codeword tables and stores that VLC lookup table in a system memory of the IHS. The VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在对位流进行解码之前对可变长度码（VLC）比特流执行预处理。比特流包括多个码字。处理器分析传入的VLC比特流信息，并生成用于存储在系统存储器或VLC码字表位置中的码字表信息。处理器从VLC码字表中的信息生成VLC查找表，并将该VLC查找表存储在IHS的系统存储器中。 VLC查找表可以通过引导零计数和位长度的可能性来呈现二维索引。

5. 发明授权

US07777653B2 Decoding variable-length code (VLC) bitstream information 有权
标题翻译：解码可变长度码（VLC）比特流信息
公开(公告)号：US07777653B2
公开(公告)日：2010-08-17
申请号：US12173192
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： An information handling system includes a processor that may perform decoding of a variable-length code (VLC) bitstream after preprocessing the bitstream. The bitstream includes multiple VLC symbols as binary codewords. The processor analyzes incoming VLC bitstream information and generates VLC codeword symbol information in conformance with a VLC lookup table. The processor may access a 2 dimensional VLC lookup table in real time or on-the-fly. The VLC lookup table may reside in a system memory of the IHS. The single VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在预处理比特流之后执行可变长度码（VLC）比特流的解码。比特流包括多个VLC符号作为二进制码字。处理器分析传入的VLC比特流信息，并根据VLC查找表生成VLC码字符号信息。处理器可以实时或即时访问二维VLC查找表。 VLC查找表可以驻留在IHS的系统存储器中。单个VLC查找表可以通过引导零计数和位长度可能性来展现二维索引。

6. 发明申请

US20100013680A1 Decoding Variable-Length Code (VLC) Bitstream Information 有权
标题翻译：解码可变长度码（VLC）比特流信息
公开(公告)号：US20100013680A1
公开(公告)日：2010-01-21
申请号：US12173192
申请日：2008-07-15
申请人： Liang Chen , Kuan Feng , Huo Ding Li , xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Liang Chen , Kuan Feng , Huo Ding Li , xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： An information handling system includes a processor that may perform decoding of a variable-length code (VLC) bitstream after preprocessing the bitstream. The bitstream includes multiple VLC symbols as binary codewords. The processor analyzes incoming VLC bitstream information and generates VLC codeword symbol information in conformance with a VLC lookup table. The processor may access a 2 dimensional VLC lookup table in real time or on-the-fly. The VLC lookup table may reside in a system memory of the IHS. The single VLC lookup table may exhibit two dimensional indexing by leading zero count and bit-length possibility.
摘要翻译：信息处理系统包括处理器，其可以在预处理比特流之后执行可变长度码（VLC）比特流的解码。比特流包括多个VLC符号作为二进制码字。处理器分析传入的VLC比特流信息，并根据VLC查找表生成VLC码字符号信息。处理器可以实时或即时访问二维VLC查找表。 VLC查找表可以驻留在IHS的系统存储器中。单个VLC查找表可以通过引导零计数和位长度可能性来展现二维索引。

7. 发明授权

US08595448B2 Asymmetric double buffering of bitstream data in a multi-core processor 有权
标题翻译：多核处理器中比特流数据的不对称双缓冲
公开(公告)号：US08595448B2
公开(公告)日：2013-11-26
申请号：US12177253
申请日：2008-07-22
申请人： Kuan Feng , Huo Ding Li , Xing S H Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Kuan Feng , Huo Ding Li , Xing S H Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： G06F12/08
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords for interpretation. The processor includes a general purpose unit (GPU) and a special purpose unit (SPU). The GPU includes GPU buffers and the SPU includes SPU buffers. After populating one GPU buffer with bitstream data, the processor populates another GPU buffer with subsequent bitstream data. The processor may populate the GPU buffers in alternating fashion. The processor populates one SPU buffer with bitstream data while parsing bitstream data in the other SPU buffer. The GPU of the processor populates the SPU buffers in alternating fashion. The size of the GPU buffers may be a multiple of the size of the SPU buffers. After the SPU buffers consume the bitstream data from one GPU buffer, the other GPU buffer transfers its bitstream data to the SPU buffers for parsing.
摘要翻译：信息处理系统包括处理可变长度码（VLC）比特流数据的多核处理器。比特流数据包括用于解释的多个码字。处理器包括通用单元（GPU）和专用单元（SPU）。 GPU包括GPU缓冲区，SPU包括SPU缓冲区。在使用比特流数据填充一个GPU缓冲器之后，处理器用随后的比特流数据填充另一个GPU缓冲器。处理器可以以交替方式填充GPU缓冲器。处理器在分析其他SPU缓冲区中的比特流数据时，使用比特流数据填充一个SPU缓冲区。处理器的GPU以交替的方式填充SPU缓冲区。 GPU缓冲器的大小可以是SPU缓冲器的大小的倍数。在SPU缓冲器从一个GPU缓冲器消耗比特流数据之后，另一个GPU缓冲器将其比特流数据传送到SPU缓冲器用于解析。

8. 发明申请

US20100023709A1 ASYMMETRIC DOUBLE BUFFERING OF BITSTREAM DATA IN A MULTI-CORE PROCESSOR 有权
标题翻译：在多核处理器中不对称双缓冲比特数据
公开(公告)号：US20100023709A1
公开(公告)日：2010-01-28
申请号：US12177253
申请日：2008-07-22
申请人： Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： G06F12/00
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords for interpretation. The processor includes a general purpose unit (GPU) and a special purpose unit (SPU). The GPU includes GPU buffers and the SPU includes SPU buffers. After populating one GPU buffer with bitstream data, the processor populates another GPU buffer with subsequent bitstream data. The processor may populate the GPU buffers in alternating fashion. The processor populates one SPU buffer with bitstream data while parsing bitstream data in the other SPU buffer. The GPU of the processor populates the SPU buffers in alternating fashion. The size of the GPU buffers may be a multiple of the size of the SPU buffers. After the SPU buffers consume the bitstream data from one GPU buffer, the other GPU buffer transfers its bitstream data to the SPU buffers for parsing.
摘要翻译：信息处理系统包括处理可变长度码（VLC）比特流数据的多核处理器。比特流数据包括用于解释的多个码字。处理器包括通用单元（GPU）和专用单元（SPU）。 GPU包括GPU缓冲区，SPU包括SPU缓冲区。在使用比特流数据填充一个GPU缓冲器之后，处理器用随后的比特流数据填充另一个GPU缓冲器。处理器可以以交替方式填充GPU缓冲器。处理器在分析其他SPU缓冲区中的比特流数据时，使用比特流数据填充一个SPU缓冲区。处理器的GPU以交替的方式填充SPU缓冲区。 GPU缓冲器的大小可以是SPU缓冲器的大小的倍数。在SPU缓冲器从一个GPU缓冲器消耗比特流数据之后，另一个GPU缓冲器将其比特流数据传送到SPU缓冲器用于解析。

9. 发明申请

US20100023708A1 VARIABLE-LENGTH CODE (VLC) BITSTREAM PARSING IN A MULTI-CORE PROCESSOR WITH BUFFER OVERLAP REGIONS 有权
标题翻译：具有缓冲区覆盖区域的多核处理器中的可变长度代码（VLC）BITSTREAM PARSING
公开(公告)号：US20100023708A1
公开(公告)日：2010-01-28
申请号：US12177232
申请日：2008-07-22
申请人： Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Kuan Feng , Huo Ding Li , Xing Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： G06F12/00
CPC分类号： G06F5/16
摘要： An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.
摘要翻译：信息处理系统包括处理可变长度码（VLC）比特流数据的多核处理器。比特流数据包括处理器组织成功能上共同的子集的多个码字。处理器包括通用处理器（GPU）和一个或多个专用处理器（SPU）。处理器的SPU可以包括两个SPU缓冲器。处理器首先将比特流数据传输到GPU缓冲存储器中，然后用比特流数据一个接一个地填充SPU缓冲器。 SPU缓冲器可以各自包括SPU用相同比特流数据填充的重叠区域。 SPU以交替的方式解析SPU缓冲器中的位流数据。当解析达到重叠区域内的子集边界时，SPU可以将解析从一个SPU缓冲区移位到另一个SPU缓冲区。

10. 发明授权

US08762602B2 Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions 有权
标题翻译：可变长度码（VLC）比特流在具有缓冲区重叠区域的多核处理器中解析
公开(公告)号：US08762602B2
公开(公告)日：2014-06-24
申请号：US12177232
申请日：2008-07-22
申请人： Kuan Feng , Huo Ding Li , Xing S H Liu , Rong Yan , Yu Yuan , Sheng Xu
发明人： Kuan Feng , Huo Ding Li , Xing S H Liu , Rong Yan , Yu Yuan , Sheng Xu
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00 , H04N7/12 , H03M7/40
CPC分类号： G06F5/16
摘要： An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.
摘要翻译：信息处理系统包括处理可变长度码（VLC）比特流数据的多核处理器。比特流数据包括处理器组织成功能上共同的子集的多个码字。处理器包括通用处理器（GPU）和一个或多个专用处理器（SPU）。处理器的SPU可以包括两个SPU缓冲器。处理器首先将比特流数据传输到GPU缓冲存储器中，然后用比特流数据一个接一个地填充SPU缓冲器。 SPU缓冲器可以各自包括SPU用相同比特流数据填充的重叠区域。 SPU以交替的方式解析SPU缓冲器中的位流数据。当解析达到重叠区域内的子集边界时，SPU可以将解析从一个SPU缓冲区移位到另一个SPU缓冲区。

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