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1. 发明申请

US20070148919A1 Multi-step epitaxial process for depositing Si/SiGe 有权
标题翻译：用于沉积Si / SiGe的多步外延工艺
公开(公告)号：US20070148919A1
公开(公告)日：2007-06-28
申请号：US11313768
申请日：2005-12-22
申请人： Li-Te Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02661
摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.
摘要翻译：一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层，使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理气体包括盐酸盐以第二流量。第一流速基本上低于第二流量。

2. 发明申请

US20070057287A1 Embedded SiGe stressor with tensile strain for NMOS current enhancement 有权
标题翻译：具有拉伸应变的嵌入式SiGe应力，用于NMOS电流增强
公开(公告)号：US20070057287A1
公开(公告)日：2007-03-15
申请号：US11227592
申请日：2005-09-15
申请人： Li-Te Lin , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te Lin , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L31/00
CPC分类号： H01L29/1083 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.
摘要翻译：提供具有局部应激源的MOS器件。本发明的实施例包括形成在衬底上的栅电极和形成在栅电极的任一侧上的源/漏区。源极/漏极区域包括嵌入的应力源和在嵌入的应力源上的覆盖层。优选地，嵌入的应力器具有大于衬底晶格间距的晶格间距。在优选实施例中，衬底是硅，并且嵌入的应力器是硅锗。还提供了一种制造方法，其中应变PMOS和NMOS晶体管可以同时形成。

3. 发明授权

US07253112B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US07253112B2
公开(公告)日：2007-08-07
申请号：US10915633
申请日：2004-08-10
申请人： Bang-Chien Ho , Jian-Hong Chen , Tsang-Jiuh Wu , Li-Te Lin , Li-Chih Chao , Hua-Tai Lin , Shyue-Sheng Lu
发明人： Bang-Chien Ho , Jian-Hong Chen , Tsang-Jiuh Wu , Li-Te Lin , Li-Chih Chao , Hua-Tai Lin , Shyue-Sheng Lu
IPC分类号： H01L21/311
CPC分类号： H01L21/76808
摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.
摘要翻译：使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料组成的通孔中形成插塞。在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。接下来，施加一层光致抗蚀剂。然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。蚀刻步骤被称为镶嵌蚀刻步骤。去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

4. 发明申请

US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
标题翻译：蚀刻过程避免多晶硅缺口
公开(公告)号：US20060154487A1
公开(公告)日：2006-07-13
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/8234 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

5. 发明申请

US20050032386A1 Etching and plasma treatment process to improve a gate profile 有权
标题翻译：蚀刻和等离子体处理工艺，提高浇口型材
公开(公告)号：US20050032386A1
公开(公告)日：2005-02-10
申请号：US10634001
申请日：2003-08-04
申请人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
发明人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/461 , H01L21/8238
CPC分类号： H01L21/823828 , H01L21/32137
摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.
摘要翻译：一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。

6. 发明申请

US20050118755A1 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US20050118755A1
公开(公告)日：2005-06-02
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

7. 发明申请

US20050014362A1 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US20050014362A1
公开(公告)日：2005-01-20
申请号：US10915633
申请日：2004-08-10
申请人： Bang-Chien Ho , Jian-Hong Chen , Tsang-Jiuh Wu , Li-Te Lin , Li-Chih Chao , Hua-Tai Lin , Shyue-Sheng Lu
发明人： Bang-Chien Ho , Jian-Hong Chen , Tsang-Jiuh Wu , Li-Te Lin , Li-Chih Chao , Hua-Tai Lin , Shyue-Sheng Lu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.
摘要翻译：使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料构成的通孔中形成插塞。在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。接下来，施加一层光致抗蚀剂。然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。蚀刻步骤被称为镶嵌蚀刻步骤。去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

8. 发明授权

US06743732B1 Organic low K dielectric etch with NH3 chemistry 失效
标题翻译：有机低K电介质蚀刻与NH3化学
公开(公告)号：US06743732B1
公开(公告)日：2004-06-01
申请号：US09769812
申请日：2001-01-26
申请人： Li-Te Lin , Li-Chih Chao , Chia-Shiung Tsai
发明人： Li-Te Lin , Li-Chih Chao , Chia-Shiung Tsai
IPC分类号： H01L21302
CPC分类号： H01L21/76811 , H01L21/31116 , H01L21/31138 , H01L21/76802 , H01L21/76813
摘要： A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast. The invention's NH3 only etch had a 30 to 80% high etch rate than N2/H2 etches of low-k materials like Silk™.
摘要翻译：仅使用NH3或NH3 / H2或NH3 / H2气体的有机低k电介质层的等离子体蚀刻工艺。在衬底上形成低k电介质层。在低k电介质层上形成掩模图案。掩模图案具有开口。使用本发明的蚀刻工艺，使用掩模图案作为蚀刻掩模，通过开口蚀刻低k电介质层。在第一实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3气体来蚀刻低k电介质层。在第二实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / H 2气体来蚀刻低k电介质层。在第三实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / N 2气体来蚀刻低k电介质层。本发明的含NH 3的等离子体蚀刻意外地快速蚀刻有机低k材料。本发明的仅NH3蚀刻具有比Silk TM的低k材料的N 2 / H 2蚀刻高30至80％的高蚀刻速率。

9. 发明授权

US06407002B1 Partial resist free approach in contact etch to improve W-filling 有权
标题翻译：接触蚀刻中的部分抗光蚀刻方法，以改善W填充
公开(公告)号：US06407002B1
公开(公告)日：2002-06-18
申请号：US09636583
申请日：2000-08-10
申请人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
发明人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/31138 , H01L21/76804 , H01L21/76829 , H01L21/76877
摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.
摘要翻译：提供了一种提高半导体衬底中的开孔的钨，W填充的方法。这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

10. 发明授权

US07390753B2 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US07390753B2
公开(公告)日：2008-06-24
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

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