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1. 发明申请

US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
标题翻译：蚀刻过程避免多晶硅缺口
公开(公告)号：US20060154487A1
公开(公告)日：2006-07-13
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/8234 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

2. 发明授权

US07109085B2 Etching process to avoid polysilicon notching 有权
标题翻译：蚀刻工艺避免多晶硅切口
公开(公告)号：US07109085B2
公开(公告)日：2006-09-19
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

3. 发明授权

US07301645B2 In-situ critical dimension measurement 有权
标题翻译：原位临界尺寸测量
公开(公告)号：US07301645B2
公开(公告)日：2007-11-27
申请号：US11053300
申请日：2005-02-07
申请人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
发明人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
IPC分类号： G01B11/02
CPC分类号： H01L22/20
摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.
摘要翻译：提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

4. 发明申请

US20060046323A1 In-situ critical dimension measrument 有权
标题翻译：原位关键维度测量
公开(公告)号：US20060046323A1
公开(公告)日：2006-03-02
申请号：US11053300
申请日：2005-02-07
申请人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
发明人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.
摘要翻译：提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

5. 发明申请

US20050118755A1 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US20050118755A1
公开(公告)日：2005-06-02
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

6. 发明授权

US07390753B2 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US07390753B2
公开(公告)日：2008-06-24
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

7. 发明申请

US20070111110A1 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US20070111110A1
公开(公告)日：2007-05-17
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： G03F1/00 , C03C15/00 , G03C5/00
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

8. 发明授权

US06407002B1 Partial resist free approach in contact etch to improve W-filling 有权
标题翻译：接触蚀刻中的部分抗光蚀刻方法，以改善W填充
公开(公告)号：US06407002B1
公开(公告)日：2002-06-18
申请号：US09636583
申请日：2000-08-10
申请人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
发明人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/31138 , H01L21/76804 , H01L21/76829 , H01L21/76877
摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.
摘要翻译：提供了一种提高半导体衬底中的开孔的钨，W填充的方法。这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

9. 发明申请

US20050106888A1 Method of in-situ damage removal - post O2 dry process 审中-公开
标题翻译：原位损伤去除方法 - 后O2干法
公开(公告)号：US20050106888A1
公开(公告)日：2005-05-19
申请号：US10714207
申请日：2003-11-14
申请人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
IPC分类号： G03F7/42 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/461 , H01L21/768
CPC分类号： H01L21/31116 , G03F7/427 , H01L21/02046 , H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814
摘要： An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.
摘要翻译：公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是可以单独使用或与上述含卤素气体中的一种一起使用。氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

10. 发明申请

US20050032386A1 Etching and plasma treatment process to improve a gate profile 有权
标题翻译：蚀刻和等离子体处理工艺，提高浇口型材
公开(公告)号：US20050032386A1
公开(公告)日：2005-02-10
申请号：US10634001
申请日：2003-08-04
申请人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
发明人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/461 , H01L21/8238
CPC分类号： H01L21/823828 , H01L21/32137
摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.
摘要翻译：一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。

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