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1. 发明授权

US07504302B2 Process of forming a non-volatile memory cell including a capacitor structure 有权
标题翻译：形成包括电容器结构的非易失性存储单元的工艺
公开(公告)号：US07504302B2
公开(公告)日：2009-03-17
申请号：US11083878
申请日：2005-03-18
申请人： Leo Mathew , Ramachandran Muralidhar , Tab A. Stephens
发明人： Leo Mathew , Ramachandran Muralidhar , Tab A. Stephens
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.
摘要翻译：非易失性存储单元可以包括衬底，覆盖衬底的有源区和覆盖衬底的电容器结构。从平面图，电容器结构围绕有源区域。在一个实施例中，非易失性存储单元包括浮置栅电极和控制栅电极。电容器结构包括第一电容器部分，第一电容器部分包括第一电容器电极和第二电容器电极。第一电容器电极电连接到浮置栅电极，并且第二电容器电极电连接到控制栅电极。用于形成非易失性存储单元的方法可以包括在衬底上形成有源区，并在衬底上形成电容器结构，其中从平面图看，电容器结构围绕有源区。

2. 发明授权

US07910482B2 Method of forming a finFET and structure 有权
标题翻译：形成finFET和结构的方法
公开(公告)号：US07910482B2
公开(公告)日：2011-03-22
申请号：US12130158
申请日：2008-05-30
申请人： Tab A. Stephens , Leo Mathew , Lakshmanna Vishnubholta , Bruce E. White
发明人： Tab A. Stephens , Leo Mathew , Lakshmanna Vishnubholta , Bruce E. White
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L29/66795 , H01L29/66818
摘要： A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.
摘要翻译：提供一种用于处理至少包括掩埋氧化物（BOX）层和半导体材料层的衬底的方法。该方法包括蚀刻半导体材料层以形成覆盖BOX层的垂直半导体材料结构，留下BOX层的暴露部分。该方法还包括将BOX层的暴露部分的顶表面暴露于抗氧化物蚀刻物质以形成覆盖BOX层的暴露部分的薄氧化物耐蚀刻层。

3. 发明授权

US07829447B2 Semiconductor structure pattern formation 有权
标题翻译：半导体结构图形形成
公开(公告)号：US07829447B2
公开(公告)日：2010-11-09
申请号：US11419304
申请日：2006-05-19
申请人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
发明人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/785 , H01L29/66795 , Y10S438/942
摘要： Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
摘要翻译：根据通过氧化可氧化材料层的侧壁形成的图案在半导体层中形成诸如翅片的结构。在一个实施例中，在可氧化层中图案化源极/漏极图案结构和鳍状图案结构。然后从在沟道图案结构的侧壁和源极/漏极图案结构的顶表面上生长氧化物的氧化过程掩蔽鳍状图案结构。随后去除沟道图案结构的剩余可氧化材料，留下氧化物层的两个部分之间的孔。这两个部分在一个实施例中用作用于图案化半导体层以形成两个散热片的掩模。该图案化还使得源极/漏极结构连接到鳍片。

4. 发明授权

US07566623B2 Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device 有权
标题翻译：形成包括具有多个栅电极的半导体鳍片的电子器件的工艺
公开(公告)号：US07566623B2
公开(公告)日：2009-07-28
申请号：US11670833
申请日：2007-02-02
申请人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
发明人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.
摘要翻译：电子设备可以包括具有与第一壁相邻的第一栅电极和与第二壁相邻的第二栅电极的半导体鳍。在一个实施例中，可以形成覆盖半导体鳍片的导电构件，并且导电构件的一部分可以反应以形成第一和第二栅电极。在另一个实施例中，可以形成图案化掩模层，其包括在栅极电极层上的掩模构件，并且可以去除覆盖在半导体鳍片上的掩蔽构件的部分。在另一个实施例中，第一鳍式晶体管结构可以包括半导体鳍片，第一和第二栅电极以及第一绝缘帽。电子器件还可以包括具有比第一绝缘盖更厚的第二绝缘帽的第二鳍式晶体管结构。

5. 发明申请

US20080274600A1 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US20080274600A1
公开(公告)日：2008-11-06
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

6. 发明授权

US06951783B2 Confined spacers for double gate transistor semiconductor fabrication process 有权
标题翻译：用于双栅晶体管半导体制造工艺的密封间隔物
公开(公告)号：US06951783B2
公开(公告)日：2005-10-04
申请号：US10695163
申请日：2003-10-28
申请人： Leo Mathew , Rode R. Mora , Bich-Yen Nguyen , Tab A. Stephens , Anne M. Vandooren
发明人： Leo Mathew , Rode R. Mora , Bich-Yen Nguyen , Tab A. Stephens , Anne M. Vandooren
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/823468 , H01L29/66628 , H01L29/66795 , H01L29/66818
摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.
摘要翻译：半导体制造工艺包括形成覆盖衬底的硅片。栅极电介质形成在鳍片的主面上。在鳍片的至少两个面上形成栅电极。然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。此后，在主翅片面上形成硅化物。在一个实施例中，栅极电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

7. 发明申请

US20090294919A1 METHOD OF FORMING A FINFET AND STRUCTURE 有权
标题翻译：形成FINFET和结构的方法
公开(公告)号：US20090294919A1
公开(公告)日：2009-12-03
申请号：US12130158
申请日：2008-05-30
申请人： Tab A. Stephens , Leo Mathew , Lakshmanna Vishnubholta , Bruce E. White
发明人： Tab A. Stephens , Leo Mathew , Lakshmanna Vishnubholta , Bruce E. White
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/02057 , H01L29/66795 , H01L29/66818
摘要： A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.
摘要翻译：提供一种用于处理至少包括掩埋氧化物（BOX）层和半导体材料层的衬底的方法。该方法包括蚀刻半导体材料层以形成覆盖BOX层的垂直半导体材料结构，留下BOX层的暴露部分。该方法还包括将BOX层的暴露部分的顶表面暴露于抗氧化物蚀刻物质以形成覆盖BOX层的暴露部分的薄氧化物耐蚀刻层。

8. 发明申请

US20080185654A1 ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN HAVING A PLURALITY OF GATE ELECTRODES AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括具有大量门电极的半导体器件的电子器件和用于形成电子器件的工艺
公开(公告)号：US20080185654A1
公开(公告)日：2008-08-07
申请号：US11670833
申请日：2007-02-02
申请人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
发明人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.
摘要翻译：电子设备可以包括具有与第一壁相邻的第一栅电极和与第二壁相邻的第二栅电极的半导体鳍。在一个实施例中，可以形成覆盖半导体鳍片的导电构件，并且导电构件的一部分可以反应以形成第一和第二栅电极。在另一个实施例中，可以形成图案化掩模层，其包括在栅极电极层上的掩模构件，并且可以去除覆盖在半导体鳍片上的掩蔽构件的部分。在另一个实施例中，第一鳍式晶体管结构可以包括半导体鳍片，第一和第二栅电极以及第一绝缘帽。电子器件还可以包括具有比第一绝缘盖更厚的第二绝缘帽的第二鳍式晶体管结构。

9. 发明申请

US20070269969A1 SEMICONDUCTOR STRUCTURE PATTERN FORMATION 有权
标题翻译：半导体结构图形成
公开(公告)号：US20070269969A1
公开(公告)日：2007-11-22
申请号：US11419304
申请日：2006-05-19
申请人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
发明人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
IPC分类号： H01L21/22 , H01L21/38 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , Y10S438/942
摘要： Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
摘要翻译：根据通过氧化可氧化材料层的侧壁形成的图案在半导体层中形成诸如翅片的结构。在一个实施例中，在可氧化层中图案化源极/漏极图案结构和鳍状图案结构。然后从在沟道图案结构的侧壁和源极/漏极图案结构的顶表面上生长氧化物的氧化过程掩蔽鳍状图案结构。随后去除沟道图案结构的剩余可氧化材料，留下氧化物层的两个部分之间的孔。这两个部分在一个实施例中用作用于图案化半导体层以形成两个散热片的掩模。该图案化还使得源极/漏极结构连接到鳍片。

10. 发明授权

US08258035B2 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US08258035B2
公开(公告)日：2012-09-04
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

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