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1. 发明授权

US08809936B2 Memory cell system with multiple nitride layers 有权
标题翻译：具有多个氮化物层的存储单元系统
公开(公告)号：US08809936B2
公开(公告)日：2014-08-19
申请号：US11461428
申请日：2006-07-31
申请人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译：提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层并且在顶部阻挡中间层上形成接触层。

2. 发明申请

US20080023750A1 MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS 有权
标题翻译：具有多层氮化物层的存储单元系统
公开(公告)号：US20080023750A1
公开(公告)日：2008-01-31
申请号：US11461428
申请日：2006-07-31
申请人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译：提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层并且在顶部阻挡中间层上形成接触层。

3. 发明授权

US07365389B1 Memory cell having enhanced high-K dielectric 有权
标题翻译：具有增强的高K电介质的存储单元
公开(公告)号：US07365389B1
公开(公告)日：2008-04-29
申请号：US11008233
申请日：2004-12-10
申请人： Joong Jeon , Wei Zheng , Mark Randolph , Meng Ding , Hidehiko Shiraiwa
发明人： Joong Jeon , Wei Zheng , Mark Randolph , Meng Ding , Hidehiko Shiraiwa
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L29/792
摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.
摘要翻译：半导体存储器件可以包括介于电荷存储层和控制栅之间的高K，高势垒高电介质材料的隔间电介质层。利用这种隔间高K，高势垒高电介质就位，可以使用Fowler-Nordheim隧道有效地擦除存储器件。

4. 发明授权

US07232724B1 Radical oxidation for bitline oxide of SONOS 有权
标题翻译： SONOS的位线氧化物的自由基氧化
公开(公告)号：US07232724B1
公开(公告)日：2007-06-19
申请号：US11113507
申请日：2005-04-25
申请人： Hidehiko Shiraiwa , Joong Jeon , Weidong Qian
发明人： Hidehiko Shiraiwa , Joong Jeon , Weidong Qian
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.
摘要翻译：公开了用于制造多位SONOS闪速存储器单元的方法，包括在晶片的衬底上形成第一介电层和电荷俘获层，并选择性地蚀刻电介质并将陷阱层电荷捕获到衬底区域以形成位线开口，然后将掺杂剂离子物质注入与位线区域中的位线开口相关联的衬底中。然后使用自由基氧化工艺在电荷俘获层上形成三层介电电荷俘获 - 电介质堆叠的第二介电层，并填充晶片的位线区域中的位线开口。最后，在三层介电 - 电荷俘获 - 电介质堆叠和晶片的位线区域之后形成字线结构。还公开了一种多位闪存阵列，其包括衬底中的位线区域，覆盖衬底的基本上邻近并基本上暴露位线区域的第一电介质层，覆盖第一电介质层的电荷俘获层，其基本上邻近于并且基本上暴露位线区域，位线氧化物隔离结构或层，其在位线区域和电荷捕获层上连续延伸，所述隔离结构包括通过自由基氧化过程形成的单个电介质材料层，以及覆盖位线氧化物隔离结构的导电字线，层。

5. 发明授权

US07446369B2 SONOS memory cell having high-K dielectric 有权
标题翻译：具有高K电介质的SONOS存储单元
公开(公告)号：US07446369B2
公开(公告)日：2008-11-04
申请号：US11196434
申请日：2005-08-04
申请人： Takashi Whitney Orimoto , Joong Jeon , Hidehiko Shiraiwa , Simon S. Chan , Harpreet K. Sachar
发明人： Takashi Whitney Orimoto , Joong Jeon , Hidehiko Shiraiwa , Simon S. Chan , Harpreet K. Sachar
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4232 , H01L29/513
摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.
摘要翻译：半导体存储器件可以包括介于浮置栅极和控制栅极之间的高K电介质材料的隔间电介质层。使用这种隔间高K电介质就可以使用Fowler-Nordheim隧道擦除存储器件。

6. 发明授权

US07196008B1 Aluminum oxide as liner or cover layer to spacers in memory device 有权
标题翻译：氧化铝作为衬垫或覆盖层与存储器件中的间隔物
公开(公告)号：US07196008B1
公开(公告)日：2007-03-27
申请号：US11087793
申请日：2005-03-23
申请人： Hidehiko Shiraiwa , Satoshi Torii , Jaeyong Park , Joong Jeon
发明人： Hidehiko Shiraiwa , Satoshi Torii , Jaeyong Park , Joong Jeon
IPC分类号： H01L21/44
CPC分类号： H01L21/76829 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al2O3 for example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.
摘要翻译：为了制造存储器件，在字线栅极的侧面形成间隔物。此外，氧化铝形成为间隔物的衬垫层或覆盖层之一。氧化铝具有例如Al 2 O 3 N 3的化学组成。这种氧化铝可以用作外围区域中的蚀刻停止层，金属硅化物块和氢块，以增强存储器件的性能。

7. 发明申请

US20070029601A1 SONOS memory cell having high-K dielectric 有权
标题翻译：具有高K电介质的SONOS存储单元
公开(公告)号：US20070029601A1
公开(公告)日：2007-02-08
申请号：US11196434
申请日：2005-08-04
申请人： Takashi Orimoto , Joong Jeon , Hidehiko Shiraiwa , Simon Chan , Harpreet Sachar
发明人： Takashi Orimoto , Joong Jeon , Hidehiko Shiraiwa , Simon Chan , Harpreet Sachar
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4232 , H01L29/513
摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.
摘要翻译：半导体存储器件可以包括介于浮置栅极和控制栅极之间的高K电介质材料的隔间电介质层。使用这种隔间高K电介质就可以使用Fowler-Nordheim隧道擦除存储器件。

8. 发明申请

US20050101147A1 Method for integrating a high-k gate dielectric in a transistor fabrication process 审中-公开
标题翻译：在晶体管制造工艺中集成高k栅极电介质的方法
公开(公告)号：US20050101147A1
公开(公告)日：2005-05-12
申请号：US10705347
申请日：2003-11-08
申请人： Catherine Labelle , Boon-Yong Ang , Joong Jeon , Allison Holbrook , Qi Xiang , Huicai Zhong
发明人： Catherine Labelle , Boon-Yong Ang , Joong Jeon , Allison Holbrook , Qi Xiang , Huicai Zhong
IPC分类号： H01L21/28 , H01L29/51 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28247 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.
摘要翻译：根据一个示例性实施例，一种在衬底上形成场效应晶体管的方法，其中衬底包括位于衬底上方的高k电介质层和位于高k电介质层上方的栅电极层，包括步骤蚀刻栅极电极层和高k电介质层以形成栅极叠层，其中栅极堆叠包括位于衬底上方的高k电介质段和位于高k电介质段上方的栅电极段。根据该示例性实施例，该方法还包括在栅极堆叠上执行氮化处理。氮化工艺可以通过例如利用等离子体来氮化栅堆叠的侧壁来进行，其中等离子体包括氮。例如，氮化处理可以使氮进入高k电介质段，并在高k电介质段中形成氧扩散阻挡层。

9. 发明授权

US06759346B1 Method of forming dielectric layers 有权
标题翻译：形成电介质层的方法
公开(公告)号：US06759346B1
公开(公告)日：2004-07-06
申请号：US10270325
申请日：2002-10-15
申请人： Joong Jeon
发明人： Joong Jeon
IPC分类号： H01L2131
CPC分类号： H01L21/31645 , C23C16/40 , C23C16/401 , C23C16/45531 , H01L21/3142
摘要： A method of forming a dielectric layer includes placing a semiconductor wafer in a reaction chamber. Oxygen, hafnium and silicon sources are separately provided to the reaction chamber to react with the wafer. After each source has reacted, a monolayer or near-monolayer film is produced. Each source may also be provided to the reaction chamber a number of times to achieve a film having the desired thickness.
摘要翻译：形成电介质层的方法包括将半导体晶片放置在反应室中。氧，铪和硅源分别提供给反应室以与晶片反应。在每个源已经反应之后，产生单层或近单层膜。也可以将各个源多次提供到反应室以实现具有所需厚度的膜。

10. 发明申请

US20080150028A1 ZERO INTERFACE POLYSILICON TO POLYSILICON GATE FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：零界面多晶硅用于半导体器件的多晶硅栅极
公开(公告)号：US20080150028A1
公开(公告)日：2008-06-26
申请号：US11614774
申请日：2006-12-21
申请人： Robert Bertram Ogle , Joong Jeon , Jon Kluth
发明人： Robert Bertram Ogle , Joong Jeon , Jon Kluth
IPC分类号： H01L29/78 , C23C16/00 , H01L21/4763
CPC分类号： H01L21/02068 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857
摘要： A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a semiconductor device. An exemplary method can include removing an oxide from a surface of a first poly layer and forming a second poly layer on the first poly layer in a processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.
摘要翻译：公开了用于处理用于半导体器件的零氧化物界面双重多晶硅结构的系统和方法。示例性的方法可以包括从第一多晶硅层的表面去除氧化物，并在处理室中的第一多晶硅层上形成第二多晶硅层。不需要从氧化物去除工具到例如多层形成工具，植入工具等的结构的转移。结果，在第一和第二多层的界面处不形成含有由第一多晶硅层暴露于含氧气氛的氧化硅的杂质。

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