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1. 发明申请

US20050101147A1 Method for integrating a high-k gate dielectric in a transistor fabrication process 审中-公开
标题翻译：在晶体管制造工艺中集成高k栅极电介质的方法
公开(公告)号：US20050101147A1
公开(公告)日：2005-05-12
申请号：US10705347
申请日：2003-11-08
申请人： Catherine Labelle , Boon-Yong Ang , Joong Jeon , Allison Holbrook , Qi Xiang , Huicai Zhong
发明人： Catherine Labelle , Boon-Yong Ang , Joong Jeon , Allison Holbrook , Qi Xiang , Huicai Zhong
IPC分类号： H01L21/28 , H01L29/51 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28247 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.
摘要翻译：根据一个示例性实施例，一种在衬底上形成场效应晶体管的方法，其中衬底包括位于衬底上方的高k电介质层和位于高k电介质层上方的栅电极层，包括步骤蚀刻栅极电极层和高k电介质层以形成栅极叠层，其中栅极堆叠包括位于衬底上方的高k电介质段和位于高k电介质段上方的栅电极段。根据该示例性实施例，该方法还包括在栅极堆叠上执行氮化处理。氮化工艺可以通过例如利用等离子体来氮化栅堆叠的侧壁来进行，其中等离子体包括氮。例如，氮化处理可以使氮进入高k电介质段，并在高k电介质段中形成氧扩散阻挡层。

2. 发明申请

US20130207108A1 Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques 有权
标题翻译：使用双重图案化技术制造的器件的关键尺寸和图案识别结构
公开(公告)号：US20130207108A1
公开(公告)日：2013-08-15
申请号：US13371585
申请日：2012-02-13
申请人： Sohan Mehta , Tong Qing Chen , Vikrant Chauhan , Ravi Srivastava , Catherine Labelle , Mark Kelling
发明人： Sohan Mehta , Tong Qing Chen , Vikrant Chauhan , Ravi Srivastava , Catherine Labelle , Mark Kelling
IPC分类号： H01L23/544 , H01L21/311 , H01L21/306
CPC分类号： H01L21/311 , H01L21/31144 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
摘要翻译：本文公开了包括多个第一线特征和多个第二线特征的说明性测试结构。在该实施例中，每个第二线特征具有第一和第二相对端，并且第一和第二线特征被布置成光栅图案，使得第一线特征的第一端对准以限定光栅结构的第一侧并且第一特征的第二端对齐以限定与光栅结构的第一侧相对的光栅结构的第二侧。第二线特征的第一端具有延伸超过光栅结构的第一侧的第一端，而第二线特征的第二端具有延伸超过光栅结构的第二侧的第一端。

3. 发明申请

US20120198403A1 MANUFACTURING FEATURES OF DIFFERENT DEPTH BY PLACEMENT OF VIAS 失效
标题翻译：通过放置VIAS制造不同深度的特征
公开(公告)号：US20120198403A1
公开(公告)日：2012-08-02
申请号：US13018551
申请日：2011-02-01
申请人： John C. Arnold , Catherine Labelle
发明人： John C. Arnold , Catherine Labelle
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L21/76808 , H01L22/12 , H01L22/20
摘要： A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.
摘要翻译：用于改变半导体晶片上的设计特征的深度的方法。通风口根据设计要求形成。也可以在相对于设计特征的位置放置不起作用的通孔。在形成通孔之后，使半导体晶片经历灰化处理，随后施加有机平坦化层。然后形成设计特征。如果设计特征的深度不符合设计要求，则可以通过改变灰化条件，有机平坦化层的选择和/或无功能和/或功能的通过放置来处理另一半导体晶片以满足设计要求。在单个半导体晶片上具有各种深度的设计特征可以用单个光刻工艺形成。

4. 发明申请

US20070072412A1 PREVENTING DAMAGE TO INTERLEVEL DIELECTRIC 审中-公开
标题翻译：防止对交流电介质的损害
公开(公告)号：US20070072412A1
公开(公告)日：2007-03-29
申请号：US11162883
申请日：2005-09-27
申请人： Derren Dunn , Nicholas Fuller , Catherine Labelle , Vincent McGahay , Sanjay Mehta , Henry Nye III
发明人： Derren Dunn , Nicholas Fuller , Catherine Labelle , Vincent McGahay , Sanjay Mehta , Henry Nye III
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/31138 , H01L21/02118 , H01L21/02123 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/76831
摘要： Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.
摘要翻译：通过在ILD中形成开口（例如，沟槽）来提供对层间电介质（ILD）的损坏的防止，并且通过在ILD内或在ILD内过度蚀刻到电介质层中，将电介质膜溅射到开口的侧壁上形成开口。再溅射的膜保护开口的侧壁不受后续的等离子体/灰分过程的影响，并且沿着侧壁和底部密封多孔电介质表面，而不影响整个工艺流程。还公开了由上述方法得到的半导体结构。

5. 发明申请

US20130224944A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS USING TAILORED CHAMFERED GATE LINER PROFILES 审中-公开
标题翻译：使用定制化的门式衬套轮廓制作集成电路的方法
公开(公告)号：US20130224944A1
公开(公告)日：2013-08-29
申请号：US13405414
申请日：2012-02-27
申请人： Puneet Khanna , Dae-han Choi , Katherina Babich , Catherine Labelle
发明人： Puneet Khanna , Dae-han Choi , Katherina Babich , Catherine Labelle
IPC分类号： H01L21/28
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.
摘要翻译：提供了使用定制的倒角门衬垫轮廓制造集成电路的方法。在一个示例性实施例中，一种用于制造集成电路的方法包括形成覆盖在半导体衬底上的伪栅电极，并在虚拟栅电极的侧壁上形成衬垫。沉积在伪栅电极，衬垫和衬底上的电介质材料。虚拟栅电极通过化学机械平面化曝光。去除虚拟栅电极的一部分，并且将衬垫各向同性地蚀刻，使其具有倒角表面。去除虚拟栅电极的其余部分以形成填充有金属的开口。

6. 发明申请

US20130181265A1 Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer 审中-公开
标题翻译：在替代栅极结构之上形成栅极盖层的方法以及包括这种栅极结构和盖层的半导体器件
公开(公告)号：US20130181265A1
公开(公告)日：2013-07-18
申请号：US13352775
申请日：2012-01-18
申请人： Gunter Grasshoff , Catherine Labelle
发明人： Gunter Grasshoff , Catherine Labelle
IPC分类号： H01L29/78 , H01L21/28 , H01L21/311
CPC分类号： H01L29/66545 , H01L21/31055 , H01L21/31116 , H01L21/3212 , H01L21/76834 , H01L21/76897
摘要： Disclosed herein are various methods of forming a gate cap layer above a replacement gate structure, and a device having such a cap layer. In one example, a device disclosed herein includes a replacement gate structure having a dished upper surface, sidewall spacers positioned proximate the replacement gate structure and a gate cap layer positioned above the replacement gate structure, wherein the gate cap layer has a bottom surface that corresponds to the dished upper surface of the replacement gate structure.
摘要翻译：这里公开了在替代栅极结构之上形成栅极盖层的各种方法，以及具有这种盖层的器件。在一个示例中，本文公开的装置包括具有碟形上表面的置换栅极结构，位于替代栅极结构附近的侧壁间隔物和位于置换栅极结构之上的栅极盖层，其中栅极盖层具有对应于到更换门结构的碟形上表面。

7. 发明授权

US07049209B1 De-fluorination of wafer surface and related structure 有权
标题翻译：晶圆表面脱氟及相关结构
公开(公告)号：US07049209B1
公开(公告)日：2006-05-23
申请号：US10907463
申请日：2005-04-01
申请人： Timothy J. Dalton , Nicholas C. M. Fuller , Kaushik A. Kumar , Catherine Labelle
发明人： Timothy J. Dalton , Nicholas C. M. Fuller , Kaushik A. Kumar , Catherine Labelle
IPC分类号： H01L21/322
CPC分类号： H01L21/31138 , H01L21/02063 , H01L21/3105 , H01L21/76814
摘要： Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.
摘要翻译：公开了在镶嵌处理之后和光致抗蚀剂去除之前脱晶晶片表面的方法，如相关结构。在一个实施例中，该方法将晶片表面放置在室中并将晶片表面暴露于来自包括氮（N 2 H 2）和/或氢（H 2 ）。曝光步骤去除晶片表面（和室）上存在的化学吸附和物理吸附的氟残基，并改善超低介电（ULK）互连结构的鲁棒性和完整性。曝光步骤由于氢和氮自由基在除去氟基物质的作用以及由于在等离子体中存在最少量的离子能量而有效。低功率密度氮和/或含氢等离子体方法使得可以忽略灰分/粘附促进剂相互作用，并降低在低k OSG基材料的双镶嵌加工过程中的集成复杂性。

8. 发明授权

US08932961B2 Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques 有权
标题翻译：使用双重图案化技术制造的器件的关键尺寸和图案识别结构
公开(公告)号：US08932961B2
公开(公告)日：2015-01-13
申请号：US13371585
申请日：2012-02-13
申请人： Sohan Mehta , Tong Qing Chen , Vikrant Chauhan , Ravi Srivastava , Catherine Labelle , Mark Kelling
发明人： Sohan Mehta , Tong Qing Chen , Vikrant Chauhan , Ravi Srivastava , Catherine Labelle , Mark Kelling
IPC分类号： H01L21/306 , H01L21/311
CPC分类号： H01L21/311 , H01L21/31144 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
摘要翻译：本文公开了包括多个第一线特征和多个第二线特征的说明性测试结构。在该实施例中，每个第二线特征具有第一和第二相对端，并且第一和第二线特征被布置成光栅图案，使得第一线特征的第一端对准以限定光栅结构的第一侧并且第一特征的第二端对齐以限定与光栅结构的第一侧相对的光栅结构的第二侧。第二线特征的第一端具有延伸超过光栅结构的第一侧的第一端，而第二线特征的第二端具有延伸超过光栅结构的第二侧的第一端。

9. 发明授权

US08901006B2 ARC residue-free etching 有权
标题翻译：无ARC残留蚀刻
公开(公告)号：US08901006B2
公开(公告)日：2014-12-02
申请号：US13081020
申请日：2011-04-06
申请人： Xiang Hu , Richard S. Wise , Habib Hichri , Catherine Labelle
发明人： Xiang Hu , Richard S. Wise , Habib Hichri , Catherine Labelle
IPC分类号： H01L21/3213 , H01L21/311 , H01L27/11 , H01L21/3105
CPC分类号： H01L23/48 , H01L21/31055 , H01L21/311 , H01L21/31111 , H01L21/3213 , H01L21/32139 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.
摘要翻译：在图案转印和后续短路过程中的抗反射残余物通过使用下面的牺牲层来确保完全去除抗反射层而消除。实施例包括在导电层（例如硅衬底）上形成硬掩模层，在硬掩模层上形成牺牲层，在牺牲层上形成光学色散层，在光学色散上形成硅抗反射涂层在硅抗反射涂层上形成光致抗蚀剂层，其中光致抗蚀剂层限定图案，蚀刻以将图案转移到硬掩模层，以及剥离至少光学色散层和牺牲层。

10. 发明授权

US08448103B2 Manufacturing features of different depth by placement of vias 失效
标题翻译：不同深度的制造功能通过放置通孔
公开(公告)号：US08448103B2
公开(公告)日：2013-05-21
申请号：US13018551
申请日：2011-02-01
申请人： John C. Arnold , Catherine Labelle
发明人： John C. Arnold , Catherine Labelle
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L21/76808 , H01L22/12 , H01L22/20
摘要： A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.
摘要翻译：用于改变半导体晶片上的设计特征的深度的方法。通风口根据设计要求形成。也可以在相对于设计特征的位置放置不起作用的通孔。在形成通孔之后，使半导体晶片经历灰化处理，随后施加有机平坦化层。然后形成设计特征。如果设计特征的深度不符合设计要求，则可以通过改变灰化条件，有机平坦化层的选择和/或无功能和/或功能的通过放置来处理另一半导体晶片以满足设计要求。在单个半导体晶片上具有各种深度的设计特征可以用单个光刻工艺形成。

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