专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110304010A1 ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE STACKING PROCESS 审中-公开
标题翻译：用于半导体器件堆叠工艺的静电放电保护方案
公开(公告)号：US20110304010A1
公开(公告)日：2011-12-15
申请号：US12851539
申请日：2010-08-05
申请人： Zhe-Wei Jiang , Ding-Ming Kwai , Shih-Hung Chen
发明人： Zhe-Wei Jiang , Ding-Ming Kwai , Shih-Hung Chen
IPC分类号： H01L23/60
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/481 , H01L23/60 , H01L24/05 , H01L24/16 , H01L24/94 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13025 , H01L2224/16145 , H01L2224/32145 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01014 , H01L2924/01046 , H01L2924/14 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect.
摘要翻译：提供了一种用于半导体器件堆叠处理的静电放电（ESD）保护方案，其中特定路径的等效电阻被设计为小于其他路径的等效电阻。因此，当半导体器件中的第一有源层和第二有源层被堆叠时，通过在这样的特定路径上设计合适的ESD保护单元，积聚在顶层晶片（或管芯）上的电荷选择这样的特定路径其他路径被释放到接地的底层晶片（或裸片）上，以达到ESD保护效果。此外，由于这样的特定路径也用作三维集成电路（3D IC）中的散热路径，所以可以降低3D IC的整体耐热性，从而提高散热效果。

2. 发明授权

US09368379B2 Systems and methods of controlling semiconductor wafer fabrication processes 有权
标题翻译：控制半导体晶圆制造工艺的系统和方法
公开(公告)号：US09368379B2
公开(公告)日：2016-06-14
申请号：US13419952
申请日：2012-03-14
申请人： Shih-Hung Chen , Ying Xiao , Chin-Hsiang Lin
发明人： Shih-Hung Chen , Ying Xiao , Chin-Hsiang Lin
IPC分类号： G06F15/00 , G01B11/26 , H01L21/67 , H01L21/68 , H01L21/687
CPC分类号： H01L21/67259 , H01L21/681 , H01L21/68764
摘要： A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly in a wafer processing module. A signal is transmitted from a signal emitter positioned at a predetermined transmission angle relative to an axis normal to the wafer support assembly to check leveling of the wafer in the module, so that the signal is reflected from the wafer. The embodiment includes monitoring for the reflected signal at a predetermined reflectance angle relative to the axis normal to the wafer support assembly at a signal receiver. A warning indication is generated if the reflected signal is not received at the signal receiver.
摘要翻译：一种控制半导体晶片制造工艺的系统和方法。该方法包括将半导体晶片定位在晶片处理模块中的晶片支撑组件上。信号从相对于垂直于晶片支撑组件的轴线以预定的传输角定位的信号发射器传输，以检查模块中晶片的调平，使得信号从晶片反射。该实施例包括在信号接收器处相对于垂直于晶片支撑组件的轴以预定的反射角监视反射信号。如果在信号接收器处未接收到反射信号，则会产生警告指示。

3. 发明授权

US09111597B2 Memory device structure with decoders in a device level separate from the array level 有权
标题翻译：存储器件结构，其中解码器的器件级别与阵列级别分开
公开(公告)号：US09111597B2
公开(公告)日：2015-08-18
申请号：US13721523
申请日：2012-12-20
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , G11C8/10 , G11C5/02
CPC分类号： G11C8/10 , G11C5/025
摘要： A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.
摘要翻译：描述了一种用于制造存储器件结构的存储器件结构和方法。存储器件结构具有设置在阵列级的存储器阵列和设置在器件级的外围电路，包括解码器和其它外围电路。存储器单元阵列具有限定在存储器单元阵列上方和下方延伸的圆柱体的周边。解码器和其它外围电路或解码器和其它外围电路的至少一部分设置在装置级内的气缸内。存储器件结构还包括垫级别中的多个焊盘。第一多个级间导电线将解码器电耦合到存储器单元阵列中的位线和字线。

4. 发明授权

US09082656B2 NAND flash with non-trapping switch transistors 有权
标题翻译： NAND闪存与非陷阱开关晶体管
公开(公告)号：US09082656B2
公开(公告)日：2015-07-14
申请号：US13294852
申请日：2011-11-11
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

5. 发明授权

US08987787B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08987787B2
公开(公告)日：2015-03-24
申请号：US13443496
申请日：2012-04-10
申请人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
发明人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
IPC分类号： H01L27/118 , H01L23/52 , H01L23/34 , H01L23/48 , H01L29/40 , H01L21/00 , H01L21/336 , H01L21/3205 , H01L23/522 , H01L23/00 , H01L25/065 , H01L25/18 , H01L27/105 , H01L27/02
CPC分类号： H01L23/522 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L27/0203 , H01L27/1052 , H01L2224/0401 , H01L2224/04042 , H01L2224/06177 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/73207 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/1431 , H01L2924/1435 , H01L2924/1443
摘要： A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
摘要翻译：半导体结构包括彼此组装的第一和第二芯片。第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。第二和第一导电线形成重叠区域。第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

6. 发明授权

US08951862B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08951862B2
公开(公告)日：2015-02-10
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

7. 发明授权

US08643078B2 Semiconductor structure and manufacturing method of the same 有权
标题翻译：半导体结构及其制造方法相同
公开(公告)号：US08643078B2
公开(公告)日：2014-02-04
申请号：US13443417
申请日：2012-04-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/788
CPC分类号： H01L23/3192 , H01L27/11565 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基极，层叠结构和掺杂层。堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和第一侧壁的长边缘沿着通道方向延伸。掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

8. 发明申请

US20130334575A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130334575A1
公开(公告)日：2013-12-19
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L27/10 , H01L21/768
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

9. 发明申请

US20130277852A1 Method for Creating a 3D Stacked Multichip Module 有权
标题翻译：创建3D堆叠多芯片模块的方法
公开(公告)号：US20130277852A1
公开(公告)日：2013-10-24
申请号：US13451411
申请日：2012-04-19
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/16146 , H01L2224/24011 , H01L2224/24146 , H01L2224/2919 , H01L2224/32145 , H01L2224/33181 , H01L2224/82031 , H01L2224/821 , H01L2224/83005 , H01L2224/83191 , H01L2224/8385 , H01L2224/9202 , H01L2225/06544 , H01L2225/06548 , H01L2225/06565 , H01L2924/00014 , H01L2224/82
摘要： A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
摘要翻译： 3D堆叠多芯片模块包括一堆W IC芯片。每个管芯具有图案化导体层，其包括与电导体的电接触区域，并且在一些示例中包括衬底上的器件电路。堆叠管芯的电导体对齐。电连接器延伸到堆叠中以接触电导体上的着陆焊盘，以产生3D堆叠多芯片模块。电连接器可以穿过电接触区域中的垂直通孔。着陆垫可以布置成阶梯式的台阶。堆叠的多芯片模块可以使用一组N个蚀刻掩模制成，其中2N-1小于W且2N大于或等于W，其中蚀刻掩模交替地覆盖并暴露每个掩模的2n-1个着陆焊盘n = 1，2。。。 N.

10. 发明申请

US20130214340A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20130214340A1
公开(公告)日：2013-08-22
申请号：US13401634
申请日：2012-02-21
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/68 , H01L21/283
CPC分类号： H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L29/7881 , H01L29/792
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基板，第一堆叠结构和第一导电层。第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式