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1. 发明申请

US20080220608A1 MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT 有权
标题翻译：通过可靠性增强的底部结构进行修改
公开(公告)号：US20080220608A1
公开(公告)日：2008-09-11
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

2. 发明授权

US07282802B2 Modified via bottom structure for reliability enhancement 有权
标题翻译：通过底部结构改进可靠性增强
公开(公告)号：US07282802B2
公开(公告)日：2007-10-16
申请号：US10964882
申请日：2004-10-14
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

3. 发明授权

US07906428B2 Modified via bottom structure for reliability enhancement 有权
标题翻译：通过底部结构改进可靠性增强
公开(公告)号：US07906428B2
公开(公告)日：2011-03-15
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

4. 发明申请

US20130175503A1 Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process 有权
标题翻译：用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）通道应变
公开(公告)号：US20130175503A1
公开(公告)日：2013-07-11
申请号：US13344352
申请日：2012-01-05
申请人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
发明人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
IPC分类号： H01L29/775 , H01L21/336 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译：提供一种制造FET器件的方法，其包括以下步骤。纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。沉积围绕纳米线的HSQ层。围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。形成一个或多个保持在纳米线中诱发的应变的栅极。还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域，其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

5. 发明授权

US06989282B2 Control of liner thickness for improving thermal cycle reliability 失效
标题翻译：控制衬套厚度，提高热循环的可靠性
公开(公告)号：US06989282B2
公开(公告)日：2006-01-24
申请号：US10815418
申请日：2004-04-01
申请人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L21/66
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译：公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。在结构中感兴趣的位置确定菌株。在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。可以根据结果进行预测和设计更改。

6. 发明授权

US08492208B1 Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process 有权
标题翻译：用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）沟道应变
公开(公告)号：US08492208B1
公开(公告)日：2013-07-23
申请号：US13344352
申请日：2012-01-05
申请人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
发明人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译：提供一种制造FET器件的方法，其包括以下步骤。纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。沉积围绕纳米线的HSQ层。围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。形成一个或多个保持在纳米线中诱发的应变的栅极。还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域，其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

7. 发明申请

US20120285517A1 SCHOTTKY BARRIER SOLAR CELLS WITH HIGH AND LOW WORK FUNCTION METAL CONTACTS 审中-公开
标题翻译： SCHOTTKY BARRIER太阳能电池具有高低功能金属接触
公开(公告)号：US20120285517A1
公开(公告)日：2012-11-15
申请号：US13103490
申请日：2011-05-09
申请人： Joel P. de Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Conal Eugene Murray , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi , Zhen Zhang
发明人： Joel P. de Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Conal Eugene Murray , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi , Zhen Zhang
IPC分类号： H01L31/108 , H01L31/18
CPC分类号： H01L31/07 , H01L31/0321 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures.
摘要翻译：一种肖特基势垒太阳能电池，其具有设置在轻掺杂的吸收材料的前表面或后表面上的低功函数区域和高功函数区域中的至少一个，其可以以各种不同的几何形状生产。生产肖特基势垒太阳能电池的方法允许短的处理时间和低温的使用。

8. 发明申请

US20080224135A1 METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY 有权
标题翻译：用于确定热循环可靠性的方法和结构
公开(公告)号：US20080224135A1
公开(公告)日：2008-09-18
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译：用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。测试结构热循环，测量结构的产量。基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

9. 发明授权

US09287186B2 Method and structure for determining thermal cycle reliability 有权
公开(公告)号：US09287186B2
公开(公告)日：2016-03-15
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58 , H01L21/66 , H01L23/522 , H01L23/00 , H05K1/09 , H05K1/02
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

10. 发明申请

US20110175211A1 Method And Structure To Reduce Soft Error Rate Susceptibility In Semiconductor Structures 有权
标题翻译：降低半导体结构中软错误率敏感性的方法和结构
公开(公告)号：US20110175211A1
公开(公告)日：2011-07-21
申请号：US12689268
申请日：2010-01-19
申请人： Cyril Cabral, JR. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
发明人： Cyril Cabral, JR. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
IPC分类号： H01L23/556 , H01L21/60 , H01L23/52 , H01L21/56
CPC分类号： H01L23/556 , H01L24/13 , H01L2924/01019 , H01L2924/01025 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/1305 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.
摘要翻译：公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到终端垫到达一个设备。

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