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1. 发明申请

US20080224135A1 METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY 有权
标题翻译：用于确定热循环可靠性的方法和结构
公开(公告)号：US20080224135A1
公开(公告)日：2008-09-18
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译：用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。测试结构热循环，测量结构的产量。基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

2. 发明授权

US07388224B2 Structure for determining thermal cycle reliability 有权
标题翻译：确定热循环可靠性的结构
公开(公告)号：US07388224B2
公开(公告)日：2008-06-17
申请号：US11502196
申请日：2006-08-10
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译：用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。测试结构热循环，测量结构的产量。基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

3. 发明授权

US07098054B2 Method and structure for determining thermal cycle reliability 失效
公开(公告)号：US07098054B2
公开(公告)日：2006-08-29
申请号：US10783462
申请日：2004-02-20
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

4. 发明授权

US09287186B2 Method and structure for determining thermal cycle reliability 有权
公开(公告)号：US09287186B2
公开(公告)日：2016-03-15
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58 , H01L21/66 , H01L23/522 , H01L23/00 , H05K1/09 , H05K1/02
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

5. 发明授权

US07345305B2 Control of liner thickness for improving thermal cycle reliability 有权
标题翻译：控制衬套厚度，提高热循环的可靠性
公开(公告)号：US07345305B2
公开(公告)日：2008-03-18
申请号：US11248719
申请日：2005-10-12
申请人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译：公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。在结构中感兴趣的位置确定菌株。在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。可以根据结果进行预测和设计更改。

6. 发明授权

US06989282B2 Control of liner thickness for improving thermal cycle reliability 失效
标题翻译：控制衬套厚度，提高热循环的可靠性
公开(公告)号：US06989282B2
公开(公告)日：2006-01-24
申请号：US10815418
申请日：2004-04-01
申请人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L21/66
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译：公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。在结构中感兴趣的位置确定菌株。在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。可以根据结果进行预测和设计更改。

7. 发明授权

US5976970A Method of making and laterally filling key hole structure for ultra fine pitch conductor lines 失效
标题翻译：超细间距导线的关键孔结构的制作和横向填充方法
公开(公告)号：US5976970A
公开(公告)日：1999-11-02
申请号：US626764
申请日：1996-03-29
申请人： Hormazdyar Minocher Dalal , Hazara Singh Rathore
发明人： Hormazdyar Minocher Dalal , Hazara Singh Rathore
IPC分类号： H01L21/768 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76877 , H01L23/53233 , H01L2924/0002
摘要： A method of forming electrical conductors having sub-half-micron geometries and using a high yield process is described. Trenches provided with an overhang are positioned where a metal interconnection is to be formed. A composite insulator layer is deposited and is followed by laterally filling with metal the trench under the overhang. Excess metal is then chem-mech polished. Only the non-crucial neck of the metal wiring is left exposed during polishing. Since spacing between the exposed metal lines is increased, it requires longer distances for the metal to smear and cause unwanted shorts. Three methods are described to laterally fill the trenches under the overhang. A first method describes the process parameters to achieve lateral deposition by high surface mobility and low sticking coefficient. A second method teaches a technique of inducing micro-creep to laterally fill the trenches under the overhang. A third method shows metal layered structures where volume expansion takes place upon phase transformation.
摘要翻译：描述了形成具有亚半微米几何形状并且使用高产量工艺的电导体的方法。设置有突出端的沟槽位于要形成金属互连的位置。沉积复合绝缘体层，然后用金属横向填充突出部下方的沟槽。然后过量的金属被化学磨光。只有金属布线的非关键颈部在抛光过程中才会露出。由于暴露的金属线之间的间距增加，所以需要更长的距离来使金属涂抹并引起不想要的短路。描述了三种方法来横向填充突出部下方的沟槽。第一种方法描述了通过高表面迁移率和低粘附系数实现横向沉积的工艺参数。第二种方法教导了一种诱导微蠕变以横向填充突出部下方的沟槽的技术。第三种方法显示了在相变时发生体积膨胀的金属层状结构。

8. 发明授权

US07163883B2 Edge seal for a semiconductor device 有权
标题翻译：半导体器件的边缘密封
公开(公告)号：US07163883B2
公开(公告)日：2007-01-16
申请号：US10694500
申请日：2003-10-27
申请人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
发明人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/8238
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76807
摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
摘要翻译：围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。电介质壁是与低k层间电介质不同的材料。

9. 发明授权

US07279411B2 Process for forming a redundant structure 有权
标题翻译：形成冗余结构的过程
公开(公告)号：US07279411B2
公开(公告)日：2007-10-09
申请号：US11164223
申请日：2005-11-15
申请人： Birendra N. Agarwala , Du Binh Nguyen , Hazara Singh Rathore
发明人： Birendra N. Agarwala , Du Binh Nguyen , Hazara Singh Rathore
IPC分类号： H01L21/4763
CPC分类号： H01L21/76847 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.
摘要翻译：装置及其制造方法。该装置包括具有金属线和通孔的双镶嵌线，以及布置成划分金属线的冗余衬垫。该方法包括在双镶嵌线的金属条中形成沟槽，在沟槽中沉积阻挡层，并用金属填充沟槽的其余部分。

10. 发明授权

US06734090B2 Method of making an edge seal for a semiconductor device 失效
标题翻译：制造半导体器件的边缘密封的方法
公开(公告)号：US06734090B2
公开(公告)日：2004-05-11
申请号：US10078861
申请日：2002-02-20
申请人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
发明人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
IPC分类号： H01L2144
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76807
摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
摘要翻译：围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。电介质壁是与低k层间电介质不同的材料。

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