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1. 发明申请

US20050262409A1 Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits 有权
标题翻译：智能捕获ATPG（自动测试模式生成）和基于扫描的集成电路的故障模拟
公开(公告)号：US20050262409A1
公开(公告)日：2005-11-24
申请号：US10850460
申请日：2004-05-21
申请人： Laung-Terng Wang , Khader Abdel-Hafez , Xiaoqing Wen , Boryau Sheu , Shun-Miin Wang
发明人： Laung-Terng Wang , Khader Abdel-Hafez , Xiaoqing Wen , Boryau Sheu , Shun-Miin Wang
IPC分类号： G01R31/28 , G01R31/30 , G01R31/3183 , G01R31/3185 , G06F11/00
CPC分类号： G01R31/318594 , G01R31/3008 , G01R31/318342 , G01R31/318364 , G01R31/318563
摘要： A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N>G>1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.
摘要翻译：一种用于产生用于以选定的扫描测试模式或选定的自测模式测试基于扫描的集成电路中的故障的刺激和测试响应的方法，所述基于扫描的集成电路包含多个扫描链，N个时钟域，和C个跨时钟域块，每个扫描链包括串联耦合的多个扫描单元，每个时钟域具有一个捕获时钟，每个交叉时钟域块包括组合逻辑网络。该方法包括将基于扫描的集成电路编译成顺序电路模型; 在移位和捕获操作期间指定基于扫描的集成电路的输入约束; 指定时钟分组以将N个时钟域映射到G个时钟域组，其中N> G> 1; 根据输入约束和时钟分组将顺序电路模型转换为等效组合电路模型; 并根据输入约束在等效组合电路模型上产生刺激和测试响应。

2. 发明申请

US20050055617A1 Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit 有权
标题翻译：用于在基于扫描的集成电路中移动高速扫描图案的方法和装置
公开(公告)号：US20050055617A1
公开(公告)日：2005-03-10
申请号：US10901298
申请日：2004-07-29
申请人： Laung-Terng Wang , Khader Abdel-Hafez , Xiaoqing Wen , Boryau Sheu , Fei-Sheng Hsu , Augusli Kifli , Shyh-Horng Lin , Shianling Wu , Shun-Miin Wang , Ming-Tung Chang
发明人： Laung-Terng Wang , Khader Abdel-Hafez , Xiaoqing Wen , Boryau Sheu , Fei-Sheng Hsu , Augusli Kifli , Shyh-Horng Lin , Shianling Wu , Shun-Miin Wang , Ming-Tung Chang
IPC分类号： G01R31/28 , G06F20060101 , H04J3/00
CPC分类号： G01R31/318594 , G01R31/318335 , G01R31/318547 , G01R31/318572 , G01R31/31905
摘要： A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division demultiplexors (TDDMs) 402, 403, decompressors 404, 405, compressors 406, 407, and time-division multiplexors (TDMs) 408, 409.
摘要翻译：时分解复用和解压缩以选定数据速率R1 421提供的压缩输入激励421的方法和装置，以选定的数据速率R2 442驱动的解压缩的刺激424,426,433,435中，用于在基于扫描的集成电路401中驱动所选择的扫描链。基于扫描的集成电路401包含高速时钟CK1 443，低速时钟CK2 442和多个扫描链411。。。 418，每个扫描链包括串联耦合的多个扫描单元。该方法和装置包括使用多个时分解复用器（TDDM）402,403和用于将刺激421和测试响应444移入和移出高速I / O焊盘的时分复用器（TDM）408,409。当应用于嵌入有一对或多对解压缩器404,405和压缩器406,407的基于扫描的集成电路401时，它可以进一步减少电路的测试时间，测试成本和扫描引脚数。还提出了一种用于合成时分解复用器（TDDM）402,403，解压缩器404,405，压缩器406,407以及时分多路复用器（TDM）408,409的合成方法。

3. 发明申请

US20050060625A1 Mask network design for scan-based integrated circuits 失效
标题翻译：基于扫描的集成电路的掩模网络设计
公开(公告)号：US20050060625A1
公开(公告)日：2005-03-17
申请号：US10876784
申请日：2004-06-28
申请人： Laung-Terng Wang , Shun-Miin Wang , Khader Abdel-Hafez , Xiaoqing Wen , Boryau Sheu
发明人： Laung-Terng Wang , Shun-Miin Wang , Khader Abdel-Hafez , Xiaoqing Wen , Boryau Sheu
IPC分类号： G01R31/28 , H01L20060101
CPC分类号： G01R31/318547 , G01R31/318536
摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.
摘要翻译：一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入。还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

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