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1. 发明申请

US20120173940A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20120173940A1
公开(公告)日：2012-07-05
申请号：US13416529
申请日：2012-03-09
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：用于在用于在系统中生成鲁棒扫描设计的设计上进行软错误保护的鲁棒扫描合成的方法在寄存器传送级（RTL）或门级选择性地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

2. 发明授权

US08161441B2 Robust scan synthesis for protecting soft errors 有权
标题翻译：用于保护软错误的强大的扫描合成
公开(公告)号：US08161441B2
公开(公告)日：2012-04-17
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G06F17/50
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

3. 发明申请

US20110022908A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20110022908A1
公开(公告)日：2011-01-27
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

4. 发明授权

US08418100B2 Robust scan synthesis for protecting soft errors 有权
标题翻译：用于保护软错误的强大的扫描合成
公开(公告)号：US08418100B2
公开(公告)日：2013-04-09
申请号：US13416529
申请日：2012-03-09
申请人： Laung-Terng Wang , Nur A. Touba , Shianling Wu , Ravi Apte
发明人： Laung-Terng Wang , Nur A. Touba , Shianling Wu , Ravi Apte
IPC分类号： G06F17/50
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：用于在用于在系统中生成鲁棒扫描设计的设计上进行软错误保护的鲁棒扫描合成的方法在寄存器传送级（RTL）或门级选择性地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

5. 发明授权

US08230282B2 Method and apparatus for low-pin-count scan compression 有权
标题翻译：低引脚数扫描压缩的方法和装置
公开(公告)号：US08230282B2
公开(公告)日：2012-07-24
申请号：US13172046
申请日：2011-06-29
申请人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

6. 发明授权

US08522096B2 Method and apparatus for testing 3D integrated circuits 失效
标题翻译：用于测试3D集成电路的方法和装置
公开(公告)号：US08522096B2
公开(公告)日：2013-08-27
申请号：US13222130
申请日：2011-08-31
申请人： Laung-Terng Wang , Nur A. Touba , Michael S. Hsiao , Zhigang Jiang , Shianling Wu
发明人： Laung-Terng Wang , Nur A. Touba , Michael S. Hsiao , Zhigang Jiang , Shianling Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318572
摘要： A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.
摘要翻译：一种使用时分解复用/复用来测试基于扫描的3D集成电路（3DIC）的方法和装置，其允许在输入/输出焊盘处施加的高数据速率扫描图案转换为应用于每个的低数据速率扫描模式嵌入模块在3DIC。提出了一套3D设计指南，以减少测试次数和预键测试和后绑定测试所需的硅通孔数（TSV）。该技术允许重新开发用于每个管芯（层）的前绑定测试的扫描模式，用于整个3DIC的后绑定测试。它进一步减少测试应用时间，而不用担心I / O焊盘计数限制和故障覆盖损失的风险。

7. 发明授权

US07996741B2 Method and apparatus for low-pin-count scan compression 有权
标题翻译：低引脚数扫描压缩的方法和装置
公开(公告)号：US07996741B2
公开(公告)日：2011-08-09
申请号：US12546060
申请日：2009-08-24
申请人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
发明人： Nur A. Touba , Laung-Terng Wang , Zhigang Jiang , Shianling Wu , Jianping Yan
IPC分类号： G01R31/28 , G06F11/00 , G06F9/455
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

8. 发明授权

US08335954B2 Method and apparatus for low-pin-count scan compression 失效
标题翻译：低引脚数扫描压缩的方法和装置
公开(公告)号：US08335954B2
公开(公告)日：2012-12-18
申请号：US13529686
申请日：2012-06-21
申请人： Nur A. Touba , Laung-Terng Wang , Shianling Wu
发明人： Nur A. Touba , Laung-Terng Wang , Shianling Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于减少测试数据量并在基于扫描的集成电路中测试应用时间的低引脚数扫描压缩方法和装置。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括可编程流水线解压缩器，其包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。可编程流水线解压缩器在其压缩扫描输入端解压缩压缩扫描模式，并将可编程流水线解压缩器的输出端上产生的解压缩扫描模式驱动到基于扫描的集成电路的扫描数据输入。由所述_combinational逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个所选故障的压缩扫描模式。

9. 发明授权

US08402328B2 Apparatus and method for protecting soft errors 有权
标题翻译：用于保护软错误的装置和方法
公开(公告)号：US08402328B2
公开(公告)日：2013-03-19
申请号：US12509019
申请日：2009-07-24
申请人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang
发明人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang
IPC分类号： G01R31/28
CPC分类号： G01R31/31816 , G01R31/318544 , G06F17/505 , G06F2217/14
摘要： An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.
摘要翻译：用于进行制造测试操作，慢速快照操作，慢速签名分析操作，速度特征分析操作，缺陷容差操作或缺陷容错操作的能力的软错误恢复或校正的装置和方法以上操作的任意组合。在一个实施例中，一种装置包括用于软错误弹性的系统电路，阴影电路和输出接合电路。耦合到系统电路和阴影电路的输出端子的输出接合电路至少包括用于缺陷容限的S元件。在另一个实施例中，一种装置包括系统电路，阴影电路，调试电路和用于软错误校正的输出连接电路。耦合到系统电路，阴影电路和调试电路的输出端子的输出接合电路至少包括用于缺陷容差的V元件。

10. 发明申请

US20110022909A1 APPARATUS AND METHOD FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软错误的装置和方法
公开(公告)号：US20110022909A1
公开(公告)日：2011-01-27
申请号：US12509019
申请日：2009-07-24
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang
IPC分类号： G01R31/3177 , G06F11/07 , G06F11/25
CPC分类号： G01R31/31816 , G01R31/318544 , G06F17/505 , G06F2217/14
摘要： An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.
摘要翻译：用于进行制造测试操作，慢速快照操作，慢速签名分析操作，速度特征分析操作，缺陷容差操作或缺陷容错操作的能力的软错误恢复或校正的装置和方法以上操作的任意组合。在一个实施例中，一种装置包括用于软错误弹性的系统电路，阴影电路和输出接合电路。耦合到系统电路和阴影电路的输出端子的输出接合电路至少包括用于缺陷容限的S元件。在另一个实施例中，一种装置包括系统电路，阴影电路，调试电路和用于软错误校正的输出连接电路。耦合到系统电路，阴影电路和调试电路的输出端子的输出接合电路至少包括用于缺陷容差的V元件。

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