专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP2665190B1 Decoding of non-binary codes with symbol re-grouping 有权
标题翻译：解码非二进制与Symbolumgruppierung码
公开(公告)号：EP2665190B1
公开(公告)日：2016-07-06
申请号：EP13163872.8
申请日：2013-04-16
申请人： LSI Corporation
发明人： Zhang, Fan , Kalluri, Madhusudan , Chang, Wu , Yang, Shaohua , Jin, Ming
IPC分类号： H03M13/11 , H03M13/37 , H03M13/29
CPC分类号： H03M13/1128 , H03M13/1171 , H03M13/2957 , H03M13/3707 , H03M13/6331 , H03M13/6343

2. 发明公开

EP2613321A3 Systems and methods for efficient parameter modification 审中-公开
标题翻译：系统和有效的参数变化的方法
公开(公告)号：EP2613321A3
公开(公告)日：2015-12-16
申请号：EP12183906.2
申请日：2012-09-11
申请人： LSI Corporation
发明人： Xia, Haitao , Yang, Shaohua , Hall, Kenneth M. , Landreth, Mark A.
IPC分类号： G11B20/18 , H04L1/20 , H04B10/079 , H04B10/077 , H04L25/03 , G11B20/10 , G11B27/36
CPC分类号： G11B27/36 , G11B20/10296 , G11B20/10509 , G11B2220/2516 , H04L1/203 , H04L25/03248 , H04L25/03318
摘要： The invention relates to a data processing system comprising: a data detector circuit (130); a data decoder circuit (170), a reliability monitor circuit (160) to calculate an error rate (225), and a parameter modification control circuit (250). Data detector circuit (130) applies a data detection algorithm to a first data set to yield a detected output (195). Data decoder circuit (170) applies a data decode algorithm to a second data set to yield the decoded output. The parameter modification circuit (250) selects a first value for a parameter and stores a first instance of the error rate corresponding to the first value; selects a second value for the parameter and stores a second instance of error count corresponding to the second value, and selects one of the first value and the second value based at least in part on a comparison of the error rates.

3. 发明公开

EP2605121A3 Systems and methods for handling out of order reporting in a storage device 有权
标题翻译：系统和用于在存储设备搬运他们的订单以外的报告方法
公开(公告)号：EP2605121A3
公开(公告)日：2015-10-14
申请号：EP12192221.5
申请日：2012-11-12
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhang, Fan , Han, Yang , Wu, Xuebin
IPC分类号： G06F3/06 , G11B20/10 , G11B20/12 , G11B20/18
CPC分类号： G06F7/24 , G06F3/0604 , G06F3/0611 , G06F3/0659 , G06F3/0674 , G11B20/10 , G11B20/12 , G11B20/18
摘要： Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device, the data storage system comprising: a host (290) operable to request an ordered data set, wherein the ordered data set includes: a first output and a second output, and wherein the first output precedes the second output in the ordered data set; a storage medium (150) maintaining the ordered data set; a data processing circuit (100) operable to access the ordered data set from the storage medium, and to process a first processing input corresponding to the first output and a second processing input corresponding to the second output to yield the first output and the second output, wherein the second output is available before the first output; and wherein the host (290) is further operable to receive the second output before the first output.

4. 发明公开

EP2637170A1 Systems and methods for data processing including pre-equalizer noise suppression 无效
标题翻译：系统与Verfahren zur Datenverarbeitung mitVorentzerrerrauschunterdrückung
公开(公告)号：EP2637170A1
公开(公告)日：2013-09-11
申请号：EP13152678.2
申请日：2013-01-25
申请人： LSI Corporation
发明人： Yang, Shaohua , Lu, Jin
IPC分类号： G11B20/10 , G11B20/18 , G11B20/12
CPC分类号： G11B20/10046 , G11B20/10379 , G11B20/1816 , G11B2020/1287 , G11B2020/183 , G11B2020/185 , G11B2220/2516 , G11B2220/415
摘要： The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.
摘要翻译：本发明涉及用于数据处理系统中预均衡器噪声抑制的系统和方法。作为示例，讨论了包括：采样平均电路，选择器电路，均衡器电路和标记检测器电路的数据处理系统。采样平均电路可操作以从码字的至少第一读取和码字的第二读取来平均对应的数据样本，以产生至少部分地基于成帧信号的平均输出。选择器电路可操作以选择平均输出和码字的第一读取中的一个作为选择的输出。均衡器电路可操作以均衡所选择的输出以产生均衡的输出，并且标记检测器电路可操作以识别均衡输出中的位置标记以产生成帧信号。

5. 发明公开

EP2605121A2 Systems and methods for handling out of order reporting in a storage device 有权
标题翻译：系统和用于在存储设备搬运他们的订单以外的报告方法
公开(公告)号：EP2605121A2
公开(公告)日：2013-06-19
申请号：EP12192221.5
申请日：2012-11-12
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhang, Fan , Han, Yang , Wu, Xuebin
IPC分类号： G06F3/06 , G11B20/10 , G11B20/12 , G11B20/18
CPC分类号： G06F7/24 , G06F3/0604 , G06F3/0611 , G06F3/0659 , G06F3/0674 , G11B20/10 , G11B20/12 , G11B20/18
摘要： Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device, the data storage system comprising: a host (290) operable to request an ordered data set, wherein the ordered data set includes: a first output and a second output, and wherein the first output precedes the second output in the ordered data set; a storage medium (150) maintaining the ordered data set; a data processing circuit (100) operable to access the ordered data set from the storage medium, and to process a first processing input corresponding to the first output and a second processing input corresponding to the second output to yield the first output and the second output, wherein the second output is available before the first output; and wherein the host (290) is further operable to receive the second output before the first output.
摘要翻译：本发明的各种实施例提供的系统和方法用于在存储设备处理无序报告，数据存储系统，包括：一个主机（290），可操作以有序数据集的请求，worin有序数据集，包括：第一输出和第二输出，和worin第一输出之前在有序数据集的第二输出; 的存储介质（150）保持的有序数据集; 一个数据处理电路（100），其可操作以访问所述有序数据从存储介质设置，并且处理第一处理输入对应于所述第一输出端和第二处理输入对应于所述第二输出，以产生所述第一输出和所述第二输出，worin第二输出是可用的第一输出之前; 和worin主机（290）是可操作的。此外，第一输出之前，接收所述第二输出。

6. 发明公开

EP2568611A2 Systems and methods for non binary decoding biasing control 审中-公开
标题翻译：用于非二进制解码偏置控制的系统和方法
公开(公告)号：EP2568611A2
公开(公告)日：2013-03-13
申请号：EP12176102.7
申请日：2012-07-12
申请人： LSI Corporation
发明人： Yang, Shaohua , Tan, Weijun , Li, Zongwang , Wang, Chung-Li , Chang, Wu , Zhang, Fan , Han, Yang
IPC分类号： H03M13/11 , H03M13/45
CPC分类号： H03M13/1102 , G11B20/10379 , G11B27/36 , G11B2220/2516 , H03M13/1111 , H03M13/3983 , H03M13/45 , H03M13/6569
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit (100) is disclosed that includes a data detector circuit (135), a biasing circuit (140), and a data decoder circuit (155). The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了包括数据检测器电路（135），偏置电路（140）和数据解码器电路（155）的数据处理电路（100）。数据检测器电路可操作用于将数据检测算法应用于一系列符号以产生检测到的输出，并且检测到的输出包括对应于非二进制符号的一系列软判决数据。偏置电路可操作地对一系列软判决数据中的每一个施加偏置以产生一系列偏置的软判决数据。数据解码器电路可操作以将数据解码算法应用于对应于非二进制符号的一系列偏置软判定数据。

7. 发明公开

EP2362395A2 Frequency-based approach for detection and classification of hard-disc defect regions 有权转让
标题翻译：经济学家安莎萨尔·埃尔法森和克里斯蒂安
公开(公告)号：EP2362395A2
公开(公告)日：2011-08-31
申请号：EP11000843.0
申请日：2011-02-03
申请人： LSI Corporation
发明人： Mathew, George , Han, Yang , Yang, Shaohua , Li, Zongwang , Lee, Yuan, Xing
IPC分类号： G11B20/18
CPC分类号： G11B20/1816 , G11B19/041 , G11B27/36
摘要： In a hard-disc drive read channel, frequency-based measures are generated at two different data frequencies (e.g., 2T and DC) by applying a transform, such as a discrete Fourier transform (DFT), to signal values, such as ADC or equalizer output values, corresponding to, e.g., a 2T data pattern stored on the hard disc. The frequency-based measures are used to detect defect regions on the hard disc and/or to classify defect regions as being due to either thermal asperity (TA) or drop-out media defect (MD).
摘要翻译：在硬盘驱动器读取通道中，通过将诸如离散付里叶变换（DFT）的变换应用于信号值（例如ADC或ADC），在两个不同的数据频率（例如，2T和DC）上生成基于频率的测量均衡器输出值，对应于例如存储在硬盘上的2T数据模式。基于频率的测量用于检测硬盘上的缺陷区域和/或将缺陷区域分类为由于热粗糙度（TA）或脱落介质缺陷（MD）引起的。

8. 发明公开

EP2650773A3 Data processing system with out of order transfer 无效转让
标题翻译：有不规则的传送数据处理系统
公开(公告)号：EP2650773A3
公开(公告)日：2016-10-19
申请号：EP13154923.0
申请日：2013-02-12
申请人： LSI Corporation
发明人： Yen, Johnson , Yang, Shaohua , Wilson, Bruce , Singleton, Jefferson E.
IPC分类号： G06F3/06 , H03M13/00 , G11B20/18 , G06F11/10
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0671 , G06F11/1076 , G11B20/1833 , G11B2020/185 , H03M13/1102 , H03M13/271 , H03M13/2778 , H03M13/2906 , H03M13/6325 , H03M13/6343
摘要： Various embodiments of the present inventions provide systems and methods for data processing with out of order transfer. For example, a data processing system is disclosed that includes a data processor operable to process input blocks of data and to yield corresponding processed output blocks of data, wherein the processed output blocks of data are output from the data processor in an order in which their processing is completed, and a scheduler (370) operable to receive processing priority requests for the input blocks of data and to assign processing resources in the data processor according to the priority requests.

9. 发明公开

EP2672483A3 Data processing system with retained sector reprocessing 有权转让
标题翻译：数据处理系统包括存储扇区的再处理
公开(公告)号：EP2672483A3
公开(公告)日：2015-09-09
申请号：EP13164619.2
申请日：2013-04-22
申请人： LSI Corporation
发明人： Yen, Johnson , Yang, Shaohua , Singleton, Jefferson E. , Wilson, Bruce , Kalluri, Madhusudan
IPC分类号： G11B20/00 , G11B20/10 , G11B20/18 , H03M13/00 , H03M13/11 , H03M13/29
CPC分类号： H03M13/1171 , G11B20/00 , G11B20/10527 , G11B20/1883 , H03M13/2957 , H03M13/6343
摘要： Various embodiments of the present inventions are related to apparatuses and methods for data processing systems with retained sector reprocessing. For example, a data processing system is disclosed that includes a data processor operable to process blocks of data and to yield corresponding processed output blocks of data, and to retain the blocks of data for reprocessing when requested, and a scheduler operable to receive reprocessing requests for the retained blocks of data and to initiate a reprocessing operation in the data processor for the retained blocks of data.

10. 发明公开

EP2670074A3 Systems and methods for data processing including EET feedback 无效
标题翻译：与EET反馈的系统和方法对数据进行处理
公开(公告)号：EP2670074A3
公开(公告)日：2014-10-29
申请号：EP13160629.5
申请日：2013-03-22
申请人： LSI Corporation
发明人： Zhang, Fan , Wang, Chung-Li , Han, Yang , Yang, Shaohua , Wu, Xuebin , Xia, Haitao , Jin, Ming
IPC分类号： H04L1/00 , H03M13/11 , H03M13/29 , H04L25/06 , H03M13/00 , H03M13/15
CPC分类号： H03M13/6331 , H03M13/1111 , H03M13/1128 , H03M13/1515 , H03M13/2957 , H04L1/005 , H04L25/061 , H04L25/067
摘要： The present invention is related to systems and methods for data processing system characterization. An embodiment of a data processing system comprises: a data processing circuit, wherein the data processing circuit includes: a data detector circuit operable to apply a data detection algorithm to a sample data set to yield a detected output; a detected output error count circuit operable to generate an output side error count corresponding to a number of errors remaining in the detected output, wherein the detected output error count circuit is operable to provide the output side error count external to the data processing circuit; a data decoder circuit operable to apply a data decoding algorithm to the detected output to yield a decoded output; and a decoded output error count circuit operable to generate an input side error count corresponding to a number of errors remaining in the decoded output, wherein the decoded output error count circuit is operable to provide the input side error count external to the data processing circuit

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式