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1. 发明专利

JP4961481B2 Bridging of serial Advanced Technology Attachment (sata) and serial-attached small computer system interface (scsi) (sas) 有权
公开(公告)号：JP4961481B2
公开(公告)日：2012-06-27
申请号：JP2009542981
申请日：2007-09-18
申请人：エルエスアイ・コーポレイションLSI Corporation
发明人：ロスジョンステンフォート，
IPC分类号： G06F3/00 , G06F13/36 , G06F13/38
CPC分类号： G06F13/4022

2. 发明专利

JP2010514063A Bridging of serial Advanced Technology Attachment (sata) and serial-attached small computer system interface (scsi) (sas) 有权
公开(公告)号：JP2010514063A
公开(公告)日：2010-04-30
申请号：JP2009542981
申请日：2007-09-18
申请人：エルエスアイ・コーポレイションLSI Corporation
发明人：ロスジョンステンフォート，
IPC分类号： G06F3/00 , G06F13/36 , G06F13/38
CPC分类号： G06F13/4022
摘要：開示される本発明の実施形態は、ＳＡＴＡ規格に準拠するように構成され、１つ以上のホストとＳＡＴＡデバイスとの間の通信をもたらす通信システムを含む。本発明の一実施形態による通信システムは、１つ以上のホストからのコマンドおよびステータスに応答するコマンドステータスマネージャ（ＣＳＭ）と、１つ以上のホストからのデータに応答して、コマンドおよびステータスのデータとは実質的に別々に、データをバッファリングするためのデータマネージャ（ＤＭ）とを有する、マルチポートブリッジデバイスを含む。

3. 发明申请

WO2015016988A1 OBJECT RECOGNITION AND TRACKING USING A CLASSIFIER COMPRISING CASCADED STAGES OF MULTIPLE DECISION TREES 审中-公开
标题翻译：使用包含多个决策阶段的分类器的分类器的对象识别和跟踪
公开(公告)号：WO2015016988A1
公开(公告)日：2015-02-05
申请号：PCT/US2014/034990
申请日：2014-04-22
申请人： LSI CORPORATION
发明人： SMIRINOV, Maxim , PUSATERI, Michael, A.
IPC分类号： G06F15/18 , G06G7/00
CPC分类号： G06K9/6282 , G06K9/00986 , G06K9/6257
摘要： An image processor comprises first and second hardware accelerators and is configured to implement a classifier. The classifier in some embodiments comprises a cascaded classifier having a plurality of stages with each such stage implementing a plurality of decision trees. At least one of the first and second hardware accelerators of the image processor is configured to generate an integral image based on a given input image, and the second hardware accelerator is configured to process image patches of the integral image through one or more of a plurality of decision trees of the classifier implemented by the image processor. By way of example, the first and second hardware accelerators illustratively comprise respective front-end and back-end accelerators of the image processor, and an integral image calculator configured to generate the integral image based on the given input image is implemented in one of the front-end accelerator and the back-end accelerator.
摘要翻译：图像处理器包括第一和第二硬件加速器，并且被配置为实现分类器。在一些实施例中，分类器包括具有多个级的级联分类器，其中每个这样的级实现多个决策树。图像处理器的第一和第二硬件加速器中的至少一个被配置为基于给定输入图像生成整体图像，并且第二硬件加速器被配置为通过多个中的一个或多个来处理积分图像的图像块由图像处理器实现的分类器的决策树。作为示例，第一和第二硬件加速器示例性地包括图像处理器的相应的前端和后端加速器，并且被配置为基于给定输入图像生成整体图像的整体图像计算器被实现在前端加速器和后端加速器。

4. 发明申请

WO2014171847A1 SYSTEM AND METHOD OF IMAGE PROCESSING 审中-公开
标题翻译：图像处理系统与方法
公开(公告)号：WO2014171847A1
公开(公告)日：2014-10-23
申请号：PCT/RU2013/000321
申请日：2013-04-16
申请人： LSI CORPORATION
发明人： ALISEITCHIK, Pavel Aleksandrovich , ZAYTSEV, Denis Vladimirovich , PARFENOV, Denis Vasilevich , LETUNOVSKIY, Aleksey Alexandrovich , BABIN, Dmitry Nicolaevich
IPC分类号： G06K9/00 , G06F3/01 , G06K9/46 , G11C7/00 , G06T1/60
CPC分类号： G06K9/00335 , G06F3/042 , G06K9/00973 , G06K9/4604 , G06K2009/4666 , G06T1/60
摘要： The disclosure is directed to a system and method of image processing. According to various embodiments of the disclosure, a storage module in communication with a plurality of memory banks stores a plurality of pixels of an image in the memory banks and interleaves the memory banks to enable a plurality of image scanners to access the plurality of pixels. A scanning module scans a selection of pixels in at least four directions relative to a first pixel of the plurality of pixels utilizing the plurality of image scanners. A singular points detection module in communication with the scanning module acquires a depth of each pixel of the selection of scanned pixels and determines a singularity value of the first pixel by comparing the depth of the first pixel with the depth of each pixel of the selection of pixels.
摘要翻译：本公开涉及一种图像处理系统和方法。根据本公开的各种实施例，与多个存储体通信的存储模块将多个像素的像素存储在存储体中并交织存储体，以使多个图像扫描器能够访问多个像素。扫描模块利用多个图像扫描仪扫描相对于多个像素中的第一像素的至少四个方向的像素选择。与扫描模块通信的奇点检测模块获取扫描像素的选择的每个像素的深度，并且通过将第一像素的深度与选择的每个像素的深度进行比较来确定第一像素的奇异值像素。

5. 发明申请

WO2014120246A1 RADIO FREQUENCY COMPOSITE CLASS-S POWER AMPLIFIER HAVING DISCRETE POWER CONTROL 审中-公开
标题翻译：具有离散功率控制的无线电频率复合类S功率放大器
公开(公告)号：WO2014120246A1
公开(公告)日：2014-08-07
申请号：PCT/US2013/024536
申请日：2013-02-02
申请人： LSI CORPORATION
发明人： WILSON, Ross S. , ABDELLI, Said E. , KISS, Peter , LATURELL, Donald R. , MACDONALD, James F.
IPC分类号： H03F1/02
CPC分类号： H03F3/2171 , H03F1/0222 , H03F1/0277 , H03F1/3241 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/217 , H03F3/2175 , H03F3/245 , H03F3/45179 , H03F3/72 , H03F2200/336 , H03F2200/387 , H03F2200/408 , H03F2200/411 , H03F2200/451 , H03F2200/504 , H03F2201/3212 , H03F2201/3233 , H03F2203/45638 , H03F2203/45731 , H03F2203/7215 , H03F2203/7236
摘要： A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal. A method of providing digitally selectable amplification includes steps of: selectively coupling a digital bitstream to a plurality of channels in the amplifier; amplifying the digital bitstream to provide an amplified signal associated with a corresponding one of the channels; filtering amplified signals associated with the channels to provide corresponding filtered signals; and combining the filtered signals to generate a composite output signal.
摘要翻译：提供数字可选择放大的复合放大器包括多个通道和组合器。每个通道包括数字可控选择器，S类功率放大器和带通滤波器。数字可控选择器选择性地将数字比特流耦合到放大器。放大器接收数字比特流并提供放大的信号。带通滤波器产生作为放大信号的函数的滤波信号。组合器将由信道提供的滤波信号耦合以形成复合输出信号。提供数字可选择放大的方法包括以下步骤：选择性地将数字比特流耦合到放大器中的多个通道; 放大数字比特流以提供与相应的一个信道相关联的放大信号; 滤波与信道相关联的放大信号以提供对应的滤波信号; 以及组合经滤波的信号以产生复合输出信号。

6. 发明申请

WO2014113028A1 CASCADED VITERBI BITSTREAM GENERATOR 审中-公开
标题翻译： CASCADED VITERBI BITSTREAM发电机
公开(公告)号：WO2014113028A1
公开(公告)日：2014-07-24
申请号：PCT/US2013/022321
申请日：2013-01-18
申请人： LSI CORPORATION
发明人： KISS, Peter , ABDELLI, Said, E. , LATURELL, Donald, R. , MACDONALD, James, F. , WILSON, Ross, S.
IPC分类号： H03M13/03
CPC分类号： H04L1/0059 , G06F17/10 , H03M7/3022 , H03M13/23 , H03M13/41
摘要： A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.
摘要翻译：比特流发生器至少包括以级联方式连接的第一和第二比特流发生器级。第一比特流发生器级包括第一加法器，其接收输入信号并产生第一误差信号，该第一误差信号指示输入信号和表示与由第一比特流产生的多个比特流候选中最接近输入信号的第一比特流候选之间的差异发电机阶段。第二比特流发生器级包括第二加法器，其接收第一误差信号并产生指示第一误差信号和第二比特流候选之间的差的第二误差信号，该第二误码信号表示与由第二比特流发生器阶段。比特流发生器中的第三加法器接收第一和第二比特流候选，并产生更近似于输入信号的输出信号。

7. 发明申请

WO2014022159A1 MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的混合格式高级冗余
公开(公告)号：WO2014022159A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/051720
申请日：2013-07-23
申请人： LSI CORPORATION
发明人： CHEN, Zhengang , WU, Yunxiang
IPC分类号： G06F11/08 , G06F12/00
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/108 , G11C29/52
摘要： Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.
摘要翻译： NVM的混合级别更高级别的冗余提供了更高级别的冗余操作，具有更好的错误恢复和/或减少的冗余信息开销。例如，以相对更多的冗余信息为代价，具有较不可靠性的诸如相对更易于出现错误的NVM的页面在具有相对更多的错误保护的较高级冗余模式中操作。同时，更具可靠性的NVM块以牺牲相对较少的冗余信息为代价的具有相对较少的错误保护的较高级冗余模式运行。与在较高级冗余模式下操作整个NVM的技术相比，具有相对更少的错误保护的技术相比，本文所述的技术提供更好的错误恢复。与在具有相对更多的错误保护的较高级冗余模式中操作NVM的整体的技术相比，本文所描述的技术提供减少的冗余信息开销。

8. 发明申请

WO2012148812A2 ENCRYPTED TRANSPORT SOLID-STATE DISK CONTROLLER 审中-公开
标题翻译：加密运输固态盘控制器
公开(公告)号：WO2012148812A2
公开(公告)日：2012-11-01
申请号：PCT/US2012/034452
申请日：2012-04-20
申请人： LSI CORPORATION , RAAM, Farbod Michael
发明人： RAAM, Farbod Michael
IPC分类号： G11C16/06 , G11C16/22 , G06F13/14 , G06F21/00
CPC分类号： G06F12/1408 , G06F21/606 , G06F21/78 , G11C16/22
摘要： An encrypted transport SSD controller has an interface for receiving commands, storage addresses, and exchanging data with a host for storage of the data in a compressed (and optionally encrypted) form in Non-Volatile Memory (NVM), such as flash memory. Encrypted data received from the host is decrypted and compressed using lossless compression for advantageously reducing flash memory write amplification. The compressed data is re- encrypted and stored in the flash memory. The stored data is retrieved, decrypted, decompressed, and re-encrypted before delivery to the host. When implemented within a secure physical boundary, such as a single integrated circuit, the SSD controller protects the encrypted data, from receipt through storage within the flash memory, including delivery to the host. In specific embodiments, the controller exchanges session encryption/decryption keys with the host and/or uses a security protocol such as TCG Opal to determine encryption/decryption keys.
摘要翻译：加密传输SSD控制器具有用于接收命令，存储地址和与主机交换数据的接口，用于以非易失性存储器（NVM）（例如闪存）中的压缩（和可选地加密的）形式存储数据。使用无损压缩解密和压缩从主机接收的加密数据，有利于减少闪存写入放大。压缩数据被重新加密并存储在闪存中。存储的数据在发送到主机之前被检索，解密，解压缩和重新加密。当在诸如单个集成电路的安全物理边界内实现时，SSD控制器通过在闪速存储器内的存储（包括传送到主机）来保护加密数据以免收到。在具体实施例中，控制器与主机交换会话加密/解密密钥和/或使用诸如TCG蛋白石之类的安全协议来确定加密/解密密钥。

9. 发明申请

WO2012109078A3 SELECTIVE ENABLEMENT OF OPERATING MODES OR FEATURES VIA HOST TRANSFER RATE DETECTION 审中-公开
公开(公告)号：WO2012109078A3
公开(公告)日：2012-08-16
申请号：PCT/US2012/023567
申请日：2012-02-02
申请人： LSI CORPORATION , TOMLIN, Andrew John
发明人： TOMLIN, Andrew John
IPC分类号： G06F13/14 , G06F13/38
摘要： Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to properly process the coalesced status information. The selective enablement disables status coalescing for a non-compliant host and enables status coalescing for at least some compliant hosts, without the SSD having prior knowledge of coupling to a non- compliant/compliant host. The SSD conservatively determines the host is non- compliant/compliant based on a negotiated speed of the serial interface, and selectively disables/enables status coalescing in response to the negotiated speed.

10. 发明申请

WO2011005249A1 SYSTEMS AND METHODS FOR TIERED NON-VOLATILE STORAGE 审中-公开
标题翻译：用于非易失性存储的系统和方法
公开(公告)号：WO2011005249A1
公开(公告)日：2011-01-13
申请号：PCT/US2009/049752
申请日：2009-07-07
申请人： LSI CORPORATION , BURGER, Harley , WARREN, Robert, W. , SHAUHUA, Yang
发明人： BURGER, Harley , WARREN, Robert, W. , SHAUHUA, Yang
IPC分类号： G06F13/10 , G06F12/00
CPC分类号： G06F12/0866 , G06F12/0897 , G06F2212/222 , G06F2212/224 , G11B5/012 , G11B5/09 , G11B20/10527 , G11B2020/1062 , G11B2220/45 , Y02D10/13
摘要： Various embodiments of the present invention provide systems and methods for tiered non-volatile storage. As an example, a multi-tiered non-volatile storage device is disclosed that includes a hard disk storage; a solid state, non-volatile storage that caches a subset of data included on the hard disk storage; and a controller circuit that is operable to control data transfer between the solid state, non-volatile storage and the hard disk storage
摘要翻译：本发明的各种实施例提供了分层非易失性存储的系统和方法。作为示例，公开了包括硬盘存储器的多层非易失性存储设备; 固态的非易失性存储器，其高速缓存包含在硬盘存储器上的数据子集; 以及可操作以控制固态，非易失性存储器和硬盘存储器之间的数据传输的控制器电路

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