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    • 5. 发明授权
    • Processor having cache structure and cache management method for elevating operation speed
    • 处理器具有缓存结构和缓存管理方法,用于提高运算速度
    • US07065612B2
    • 2006-06-20
    • US10396154
    • 2003-03-25
    • Sung-bae Park
    • Sung-bae Park
    • G06B12/00
    • G06F9/3802G06F9/3861G06F12/0848
    • A processor having a cache memory structure which improves an operation speed of the processor and a method of managing cache memory of the processor are provided. The cache memory is divided into a cache memory for normal programs which stores instructions required for running normal programs and a cache memory for exception programs. An instruction register fetches and stores instructions from one of the cache memories according to the type of program currently running. The method includes dividing the cache memory into a cache memory for normal programs and a cache memory for exception programs, storing instructions and/or data for running the normal and exception programs in their respective cache memories, determining a type of a currently running program, fetching instructions from either cache memory according to the type of program currently running, and inputting the fetched instructions to the instruction register.
    • 提供具有提高处理器的操作速度的高速缓存存储器结构的处理器和管理处理器的高速缓冲存储器的方法。 高速缓冲存储器被分成用于正常程序的高速缓存存储器,其存储用于运行正常程序所需的指令和用于异常程序的高速缓冲存储器。 指令寄存器根据当前运行的程序的类型从一个缓存存储器中取出并存储指令。 该方法包括将高速缓冲存储器划分为用于正常程序的高速缓冲存储器和用于异常程序的高速缓冲存储器,存储用于在它们各自的高速缓冲存储器中运行正常和异常程序的指令和/或数据,确定当前正在运行的程序的类型, 根据当前运行的程序的类型从任一高速缓冲存储器读取指令,并将读取的指令输入到指令寄存器。