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1. 发明授权

US07911001B2 Methods for forming self-aligned dual stress liners for CMOS semiconductor devices 有权
标题翻译：用于形成用于CMOS半导体器件的自对准双应力衬垫的方法
公开(公告)号：US07911001B2
公开(公告)日：2011-03-22
申请号：US11778045
申请日：2007-07-15
申请人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
IPC分类号： H01L21/311 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
摘要翻译：提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

2. 发明申请

US20090014808A1 Methods For Forming Self-Aligned Dual Stress Liners For CMOS Semiconductor Devices 有权
标题翻译：用于形成CMOS半导体器件的自对准双重应力衬垫的方法
公开(公告)号：US20090014808A1
公开(公告)日：2009-01-15
申请号：US11778045
申请日：2007-07-15
申请人： Kyoung-Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
发明人： Kyoung-Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
IPC分类号： H01L27/092 , H01L21/311
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
摘要翻译：提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

3. 发明申请

US20110163387A1 METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于形成用于CMOS半导体器件的自对准双应力衬片的方法
公开(公告)号：US20110163387A1
公开(公告)日：2011-07-07
申请号：US13050219
申请日：2011-03-17
申请人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
摘要翻译：提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

4. 发明授权

US07790622B2 Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes 有权
标题翻译：在CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US07790622B2
公开(公告)日：2010-09-07
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

5. 发明申请

US20090017625A1 Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes 有权
标题翻译： CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US20090017625A1
公开(公告)日：2009-01-15
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

6. 发明授权

US07598572B2 Silicided polysilicon spacer for enhanced contact area 失效
标题翻译：用于增强接触面积的硅化多晶硅间隔物
公开(公告)号：US07598572B2
公开(公告)日：2009-10-06
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L29/40
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

7. 发明申请

US20080102612A1 SILICIDED POLYSILICON SPACER FOR ENHANCED CONTACT AREA 失效
标题翻译：用于增强接触面积的多孔聚硅氧烷绝缘子
公开(公告)号：US20080102612A1
公开(公告)日：2008-05-01
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L21/44 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

8. 发明申请

US20130001660A1 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 失效
公开(公告)号：US20130001660A1
公开(公告)日：2013-01-03
申请号：US13615955
申请日：2012-09-14
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

9. 发明授权

US08063449B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08063449B2
公开(公告)日：2011-11-22
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

10. 发明授权

US07989357B2 Method of patterning semiconductor structure and structure thereof 有权
标题翻译：图案化半导体结构及其结构的方法
公开(公告)号：US07989357B2
公开(公告)日：2011-08-02
申请号：US11950741
申请日：2007-12-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L23/48
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

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